【Synopsys武汉】招Sr, CAE（模拟/数字设计）

synopsys_hire

Hi All,

Synopsys武汉热招Sr CAE，具体JD如下，欢迎有意向的朋友发送简历到qyzhong@synopsys.com

Provide technical support to customers for integration of Synopsys’ Mixed Signal IP into ASICs.  This includes:

• Debugging of customers’ simulation or silicon issues.
• Reviewing customers’ integration of our IP.
  • Logical and Physical integration.
• Answering technical questions about our IPs’ operation and features.
• Train field engineers in IP operation and demonstration.
• Interface with R&D and Product Engineering teams to provide timely communication to and from customers.

Qualifications:

• BS +5 years of prior work-experience, or MS +3 years of prior work-experience.

Must-Have Skills:

• All front-end skills:
  • RTL design & verification in Verilog, Synthesis, Static-Timing Analysis, DFT, CDC.
• Scripting in Perl/TCL/Python etc..
• Time management skills to balance multiple high-priority tasks and projects.
• Excellent oral and written communication skills.
• Willingness to learn new skills and perform tasks that often go outside of the area of current expertise.

Skills that will put you at an advantage:

• Domain-knowledge : High-speed serial communication standards like USB2.0, HSIC, USB3.0, USB3.1, Type-C, Alternate mode etc.., with full understanding of functional partitioning between protocol layers.
• Back-end skills.
  • DRC, LVS, ERC, PERC, understanding of double patterning.
• Analog design/simulation.
  • HSPICE, XA-RA.
• Understanding of transmission-line fundamentals, and signal-integrity concepts.
• Lab experience.
  • Familiarity with ATE concepts and test program flow.
  • Familiarity with bench-level and compliance testing.

synopsys_hire

update

aftertree

做过一两年FPGA，主要应用是控制方面，没有做过相关设计可以吗？

synopsys_hire

回复 3# aftertree


    欢迎发送简历到qyzhong@synopsy.com

synopsys_hire

update

synopsys_hire

欢迎发送简历到qyzhong@synopsy.com