【Synopsys上海/深圳】热招Sr, CAE

synopsys_hire

Hi all,

Synopsys上海/深圳招Sr,CAE，具体JD如下，欢迎有意向的朋友发送简历到qyzhong@synopsys.com

此职位为MIPI/HDMI PHY IP的CAE职位，欢迎模拟设计、数字前端设计/验证的朋友投递简历！

上海：长宁路1027号兆丰广场13~18楼（地铁中山公园站7号出口）

Synopsys® is a leading provider of high-quality, silicon-proven IP solutions for Systems-on-Chip (SoC) designs.

DesignWare® MIPI® IP solutions enable the interface between system-on-chips (SoCs), application processors, baseband processors and peripheral devices. They include a broad portfolio of controllers, silicon-proven PHYs, Verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems. As an active contributor to the MIPI Alliance working groups, Synopsys continues to play a key role in supporting the mobile ecosystem by developing high-quality, interoperable MIPI IP solutions that enable designers to deploy new features into their next-generation mobile devices.

DesignWare® HDMI Transmitter (TX) and Receiver (RX) IP solutions provide the necessary logic to implement and verify designs for various consumer electronic applications. With multiple design wins and products shipping in volume, the power- and area-optimized DesignWare® HDMI TX and RX IP solutions are compliant with the latest HDMI specifications and have gone through extensive in-house and third-party interoperability testing. The complete HDMI IP solutions consisting of digital controllers, PHYs and verification IP as well as IP Prototyping Kits with associated software and drivers, enable SoC designers to accelerate time-to-market and lower IP integration


Responsibilities:

As a Corporate Applications Engineer (CAE), you will be involved in providing technical support to field engineers and customers who are using or considering Synopsys’ MIPI PHY and HDMI PHY Intellectual Property (IP). You will have the capability to design and guide customers to implement solutions to complex applications problems independently with little guidance. You will partner with high-tech customers through the full-cycle of ASIC design from installation, training and RTL design to production testing. Authoring application-notes and/or white-papers that promote the IPs’ ease of use, or address specific challenges in the IPs’ usage will also be a responsibility. You will have regular contact with external customers and internal contacts across cross-functional and international teams.


Requirements:

• Minimum of 5 years related experience.
• Strong understanding of the ASIC design process.
• Working knowledge in Verilog HDL, Synthesis, Simulation, Verification.
• Knowledge in Place and Route, Design Reuse and/or Physical Design or Analog Design will be an added advantage.
• High-speed SERDES interfaces knowledge is a plus.
• Strong communication skills – verbal and written are a must.
• Ability to interact with customers as well as peers, highly independent with a “can-do” attitude.
• Willing to learn new skills and perform tasks that often go outside of the area of current expertise.

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synopsys_hire

招MIPI IP CAE了~欢迎数字前端IP（不局限何种IP，如有接口类IP经验更佳）的朋友投递简历！

synopsys_hire

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