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module hist(clk,rst,im_input,im_output);
input clk;
input rst;
input [7:0] im_input;
output [7:0] im_output;
reg [7:0] im_output;
reg [14:0] hist_cnt [0:255]; //灰度计数，存入RAM
reg [14:0] hist_acc [0:255]; //灰度累加
reg [7:0] mem [0:16383]; // 存储像素值
reg [7:0] reshape[0:255]; //重新定义的灰度
reg[24:0] acul_reg;
reg [7:0] out_reg;
reg hist_cnt_en,hist_acc_en,cal_en,cal_over;
reg [14:0] i;
reg [8:0] j;
reg [8:0] k;
reg [14:0] l;
integer index;
parameter rate=10'b11_1111_1011;
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
for(index=0; index<9'd256; index=index+1)
begin
hist_cnt[index]<=0;
hist_acc[index]<=0;
end
end
end
always @ (posedge clk or negedge rst)
begin
if(!rst)
begin
i<=0;
j<=1;
k<=0;
l<=0;
hist_cnt_en<=1;
hist_acc_en<=0;
cal_en<=0;
cal_over<=0;
end
else if(hist_cnt_en==1)
begin
mem[i]<=im_input;
hist_cnt[im_input]<=hist_cnt[im_input]+1;
i<=i+1;
if(i==16384)
begin
hist_cnt_en<=0;
hist_acc_en<=1;
cal_en<=0;
cal_over<=0;
hist_acc[0]<=hist_cnt[0];
end
end
else if(hist_acc_en<=1)
begin
hist_acc[j]<=hist_acc[j-1]+hist_cnt[j];
j<=j+1;
if(j==256)
begin
hist_cnt_en<=0;
hist_acc_en<=0;
cal_en<=1;
cal_over<=0;
end
end
else if(cal_en==1)
begin
acul_reg<=hist_acc[k]*rate;
reshape[k]<=acul_reg[23:16];
k<=k+1;
if(k==256)
begin
hist_cnt_en<=0;
hist_acc_en<=0;
cal_en<=0;
cal_over<=1;
end
end
else if(cal_over==1)
begin
out_reg<=reshape[mem[l]];
im_output<=out_reg;
l<=l+1;
if(l==16384)
begin
hist_cnt_en<=1;
hist_acc_en<=0;
cal_en<=0;
cal_over<=0;
end
end
end
endmodule
综合时出现问题：Map:116 - The design is empty. No processing will be done.
ERROR:Map:52 - Problem encountered processing RPMs.
感觉不知道是哪里出了问题 |
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2016-7-5 19:01:41
