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//-----------------------------------------------//
//按字复用，8M的TDM码流顺序为
//第一路TS0，第二路TS0，第三路TS0，第4路TS0;
//第一路TS1，第二路TS1，第三路TS1，第4路TS1;
// ............................. ...
//第一路TS31，第二路TS31，第三路TS31，第四路TS31;
//分为4路2M的PCM 第一路TS0，TS1.............TS31;
// 第二路TS0，TS1.............TS31;
// 第三路TS0，TS1.............TS31;
// 第四路TS0，TS1.............TS31;
//----------------------------------------------//
`timescale 10ns/1ns
module fenpin(clk,rst,clk8m,pcm1,pcm2,pcm3,pcm4,
clk2m,clk8k,datain,out1,out2);
input clk,rst,datain;
output clk8m,clk2m,clk8k,pcm1,pcm2,pcm3,pcm4,out1,out2;
reg[3:0] cnt1,cnt4;
reg[9:0] cnt5;
reg clk8m,clk2m,clk8k,pcm1,pcm2,pcm3,pcm4;
reg[7:0] indata0[3:0];
reg[7:0] outdata[3:0];
reg[7:0] tem_8m,tem_2m;
reg[7:0] data2m1,data2m2,data2m3,data2m4;
reg[7:0] tem1,tem2,tem3,tem4,mem1,mem2,mem3,mem4;
parameter data0=8'b00000000;
reg clk4m,clk5bk,clk1m,clk125;
reg[2:0] cnt,cnt3,addr;
reg[1:0] cnt6,cnt2,num;
reg[3:0] count,cnt7,cnt8;
reg numb1;
//reg[1:0] num;
//integer i,j,k,l;
initial
begin
cnt3=3'b000;
numb1=1'b0;
cnt=3'b000;
count=4'b0000;
// cnt7=4'b0000;
num=2'b00;
// cnt8=4'b0000;
addr=3'b000;
// i=0;
// j=0;
// k=0;
// l=0;
end
//--------------------------------8MHz---
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
clk8m<=0;
cnt1<=0;
end
else
begin
if(cnt1==4'b0010)
begin
clk8m<=~clk8m;
cnt1<=0;
end
else
cnt1<=cnt1+1'b1;
end
end
//------------------------------2MHz------
always @(posedge clk8m or negedge rst)
begin
if(!rst)
begin
clk2m<=1;
clk4m<=1;
cnt2<=0;
end
else
begin
clk4m<=~clk4m;
if(cnt2==2'b01)
begin
clk2m<=~clk2m;
cnt2<=0;
end
else
cnt2<=cnt2+1'b1;
end
end
//----------------------------500k/1m---------
always @(posedge clk2m or negedge rst)
begin
if(!rst)
begin
cnt6<=0;
clk5bk<=0;
clk1m<=1;
end
else
begin
clk1m<=~clk1m;
if(cnt6==2'b11)//01,clk500k
begin
clk125<=~clk125;
cnt6<=0;
end
else
begin
cnt6<=cnt6+1'b1;
end
end
end
//-----------------------------clk8khz-----
always @(posedge clk2m or negedge rst)
begin
if(!rst)
begin
cnt5<=0;
clk8k<=0;
end
else if(cnt5==10'b0011111001)//10'b1111100111---8m;10'b0011111001---2m
begin
clk8k<=1;
cnt5<=0;
end
else
begin
clk8k<=0;
cnt5<=cnt5+1'b1;
end
end
//-----------------------采集8K脉冲---
always @(posedge clk8k)
begin
if(clk8k&clk2m)
numb1<=1'b1;
else
numb1<=0;
end
//end
// ----------------------串转并---
always @(posedge clk8m)
begin
if(numb1==1)
begin
tem_8m[0]<=clk4m;
tem_8m[1]<=tem_8m[0];
tem_8m[2]<=tem_8m[1];
tem_8m[3]<=tem_8m[2];
tem_8m[4]<=tem_8m[3];
tem_8m[5]<=tem_8m[4];
tem_8m[6]<=tem_8m[5];
tem_8m[7]<=tem_8m[6];
cnt3<=cnt3+1'b1;
end
if(cnt3==3'b111)
begin
indata0[addr]<=tem_8m[7:0];
// tem_2m[7:0]<=tem_8m[7:0];
cnt3<=0;
addr<=addr+1'b1;
cnt<=cnt+1'b1;
end
if(addr==3'b100)
addr<=0;
if(cnt==3'b101)
cnt<=0;
end
//-------------------------------
assign out1=clk1m;
assign out2=clk125;
//------------------------------
always @(posedge clk2m)
begin
case(cnt)
3'b001:begin
data2m1<=indata0[0];
tem1<=data2m1+1'b1;
end
3'b010:begin
data2m2<=indata0[1];
tem2<=data2m2;
end
3'b011:begin
data2m3<=indata0[2];
tem3<=data2m3;
end
3'b100:begin
data2m4<=indata0[3];
tem4<=data2m4+1'b1;
end
default:;
endcase
end
//----------------------------------------
always @(posedge clk2m)
begin
mem1[7:1]<=mem1[6:0];
mem2[7:1]<=mem2[6:0];
mem3[7:1]<=mem3[6:0];
mem4[7:1]<=mem4[6:0];
count<=count+1'b1;
if(count==4'b0111)
begin
count<=4'b0000;
mem1<=tem1;
mem2<=tem2;
mem3<=tem3;
mem4<=tem4;
end
pcm1<=mem1[7];
pcm2<=mem2[7];
pcm3<=mem3[7];
pcm4<=mem4[7];
end
endmodule |
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创芯大讲堂
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发表于 2016-6-27 09:37:11
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