NVIDIA英伟达职位：ASIC Physical Design engineer

NVHR

在二十年的时间里，NVIDIA 一直在视觉计算方面 (计算机图形的艺术与科学) 勇当先锋。

凭借我们发明的 GPU ——现代视觉计算的引擎，这一领域现已扩张到涵盖了视频游戏、电影制作、产品设计、医学诊断以及科学研究等等。

现在，视觉计算正变得越来越重要，它影响着人们与科技之间的互动方式。

NVIDIA坚信我们的领先地位是来自於优秀员工的贡献，毋庸置疑，我们将以最佳方式发掘杰出的人才。NVIDIA人力资源团队矢志为NVIDIA员工提供持续的训练和成长。在热衷学习的环境中，我们的终极目标是创造员工和公司的双赢。如果您笃信并服膺於创新丶智识的诚信丶直接和坦率丶团队合作以及工作高标准，请加入我们，您正是我们正在寻找的人才。

请将个人简历或者联系方式寄至elainew@nvidia.com信箱，我们将由专人与您联系。

ASIC Physical Design Team 的主要工作内容分为两大部分，芯片物理整合和时序分析及其修正。

这个工作有两个突出的特点

1.接触面广。
有机会接触了解到从前端设计到后端流片的各个环节。

2.有专长的知识，物理整合和时序分析需要对综合，网表质量检查，形式验证，芯片整体的物理需求有深入的了解。同时对静态时序分析，时钟结构的调整和优化，功耗的优化有深入的了解。

NVIDIA的芯片规模大，工艺先进。这给我们的工作带来了极大的挑战。对个人来说也有机会学习到最领先的芯片设计知识和方法。

不同于其他的海外团队，Shanghai ASIC-PD 团队是全球团队中的核心成员。已经独立完成了多块芯片的物理整合和时序分析。技术水平在全球团队中处于领先地位。

上海：

ASIC Physical Design engineer



As asenior member of our ASIC-PD team, you'll be working on streamlining the chipinfrastructure process across product designs, focusing on full chip layoutplanning (partitioning, planning clock distribution and other structure,methodology), partition/full chip timing closure (primetime scripts, othertools, etc) and gate-level design of high-speed logic

RESPONSIBILITIES:

·
Chip integration and netlist generation

-Synthesis, Formal verification, netlistquality check
Work in conjunction with Place and RouteEngineers to achieve timing closure for both partition level and full chiplevel
Develop and enhance entire timing flow fromfrontend (pre-layout) to backend (post-layout) at both chip and block level.
Develop custom timing scripts usingtcl/primetime for clock skew analysis, special circuits such as clock dividers,core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory,TMDS, etc.
Develop flow to physically partition andfloorplan the entire chip.
Developscripts for performing ECO's.

MINIMUM REQUIREMENTS:

·
BS or MS in Electrical Engineering or ComputerScience
Above 3 years of relevant ASIC experienceideally with a focus in the chip integration /synthesis/formal and timingclosure

（Open for both junior and senior candidate.）
- Excellent scripts skills
- Excellent written and verbal communicationskills in English
- Ability to multiplex many issues, setpriorities, and work in a team environment
- Keep up to date with leading edgetechnologies

NVHR

up~~~

有意者欢迎联络！ elainew@nvidia.com

NVHR

up~~~

有意者欢迎联络！ elainew@nvidia.com

mylove2

回复 3# NVHR


   全是乱码

NVHR

回复 4# mylove2


    As a senior member of our ASIC-PD team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic

RESPONSIBILITIES:
&#8226;    Chip integration and netlist generation
&#8226;    -Synthesis, Formal verification, netlist quality check
&#8226;    Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level
&#8226;    Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
&#8226;    Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
&#8226;    Develop flow to physically partition and floorplan the entire chip.
&#8226;     Develop scripts for performing ECO's.


MINIMUM REQUIREMENTS:
&#8226;    BS or MS in Electrical Engineering or Computer Science
&#8226;    Above 3 years of relevant ASIC experience ideally with a focus in the chip integration /synthesis/formal and timing closure
&#8226;    - Excellent scripts skills
&#8226;    - Excellent written and verbal communication skills in English
&#8226;    - Ability to multiplex many issues, set priorities, and work in a team environment
&#8226;    - Keep up to date with leading edge technologies

NVHR

up~~~

有意者欢迎联络！ elainew@nvidia.com

mylove2

回复 5# NVHR

S or MS in Electrical Engineering or ComputerScience
Above 3 years of relevant ASIC experienceideally with a focus in the chip integration /synthesis/formal and timingclosure

（Open for both junior and senior candidate.）
- Excellent scripts skills

夏晓芸0901

招应届生吗

NVHR

up~~~

有意者欢迎联络！ elainew@nvidia.com

NVHR

回复 8# 夏晓芸0901

理论上不招，如果特别优秀和Match的也可以考虑。 ^ ^