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本帖最后由 petrel87 于 2016-6-1 14:22 编辑
我前仿过了。后仿现在还没加sdf(理想条件下),出现x态。考虑是不是warning导致的内部逻辑不通。
现在把各种警告贴上来,求指点,困扰我好久了。
哪些警告是必须消除的。。。
第一种:20处左右:Warning: Undriven register 'r_reg[MEMO][DATAOUT][16]' is connected to primary output 'r_out[MEMO][DATAOUT][16]'. (ELAB-832)
第二种:1处:Warning: ./encode.vhd:103: DEFAULT branch of CASE statement cannot be reached. (ELAB-311)
第三种:50处:Warning: In design 'rt1553', cell 'C22054' does not drive any nets. (LINT-1)
第四:800多处。。。Warning: In design 'rt1553', port 'r_out[BLOCK_CIR_ADDRESS][15]' is not connected to any nets. (LINT-28)
第五:70处: Warning: In design 'rt1553', output port 'memi[DATAIN][15]' is connected directly to output port 'r_out[MEMI][DATAIN][15]'. (LINT-31)
第六:3处:Warning: In design 'TOP1553', a pin on submodule 'memory' is connected to logic 1 or logic 0. (LINT-32)
Pin 'read_b' is connected to logic 1.
第七:90处: Warning: In design 'TOP1553', net 'memory/data5[0]' has multiple drivers (unknown wired-logic type). (LINT-38)
第八:1处: Warning: Design 'TOP1553' contains 8 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
第九:1处: Warning: DesignWare synthetic library dw_foundation.sldb is added to the synthetic_library in the current command. (UISN-40)
第十:150处: Warning: Unable to determine wired-logic type for multiple-driver net 'memory/data1[12]'. (TRANS-5)
Information: Assuming multiple-driver net 'memory/data1[12]' is a wired-AND. (TRANS-6)
Warning: Unable to determine wired-logic type for multiple-driver net 'memory/data1[13]'. (TRANS-5)
第十一:5000多处: Warning: Target library contains no replacement for register 'regs/r_sys_reg[MUX1M_10M]' (**FFGEN**). (TRANS-4)
另外。。。因为有个dpram模块,我使用了shared variable,是不是会导致不可综合啊?
elabrate之前的error: 不知道是不是有影响
Error: Cannot create procedure named 'group_variable' - existing command
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