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[招聘] Conxant(科胜讯) 成都/上海最新职位需求【2016-05-16】

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发表于 2016-5-14 19:52:38 | 显示全部楼层 |阅读模式

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本帖最后由 dfb211 于 2016-5-14 20:10 编辑

公司介绍: conexant(科胜讯)成都,总部在加州的尔湾,在台北,上海,成都都有研发中心,现在主要从事音频芯片和FAX/Modem芯片的开发。成都研发中心主要负责音频芯片、硬件、软件和驱动开发。公司工作自由,早晚不打卡,周末不加班,但不代表里面的员工是在混日子的,公司的性质决定了这里需要高效高能高产出的工程师。如果你希望多点时间照顾家庭而又对工作充满期待,这里值得你一试。至于待遇,这个真的要靠自己争取,但我能说的是不会让你失望的。

请同行有想换工作环境的同仁联系小弟,因为内推,将优先保障机会。

用的是公司邮箱,如果同事看到请勿在论坛喷,到我的座位来喷吧,哈哈,你懂的。
Danbo.Deng@conexant.com

有什么疑问也可以通过发邮件问我,大多数时候都不在关注论坛。

职位要求比较简单,在行业里面混久了,都能触类旁通,所以不要对职位要求太担心,

Job Title: ASIC Verification Engineer

Location : Chengdu

Target Candidate:   Experienced in ASIC verification.

Minimum Experience: 3+ years

Key Areas of Responsibilities

-Write verification plans according to architecture document

-Writing behavioral models, monitors, and self-checking test benches

Required Skills and Attributes

-Experience of Verilog, SystemVerilog, UVM

-Hands on experience of SOC architecture, micro-processor verification, and silicon debug environment"




Job Title: Senior Analog Mixed-Signal Design Engineer

Location : Chengdu

Target Candidate:  Experienced CMOS analog/mixed-signal circuit design

Minimum Experience: 3+ years"

Key Areas of Responsibilities:

-Design of high-performance low-power data converters, analog front-ends and power management blocks.

-Participate in product definition, implementation, verification, and lab validation

Required Skills and Attributes

-Expert knowledge in high resolution sigma-delta A/D and D/A converters, Class-D PWM amplifiers, DC/DC converters.

-Expert knowledge in transistor-level analog CMOS design fundamentals, including operational amplifiers, continuous-time and discrete-time circuits

-Strong knowledge in signal processing fundamentals




Job Titleayout Engineer

Location : Chengdu

Target Candidate:  Experienced in Layout design

Minimum Experience: 3+ years

Key Areas of Responsibilities:

-Analog Mixed Signal Layout Engineer who has extensive experience in analog circuit layout, ADC, DAC, PLL, PAD etc.

Required Skills and Attributes

-3+ years of mask layout experience working advanced nodes

-3+ years of experience with Virtuoso, caliber, etc.





-Full chip DRC and LVS experience




Job Title : Hardware Design Engineer

Location  : Chengdu

Target Candidate:  Experienced in  Hardware design

Minimum Experience: 3+ years

Key Areas of Responsibilities:

-Write hardware design specification and Design schematics and  layout.

-Debug and solve any issue during the development

-Audio or acoustic design/integration and tuning to provide compelling end user experience

Required Skills and Attributes

-Hardware design experience on digital and analog circuits

-Be familiar with power supply system, clock system and interface standards (I2C, USB, SPI, Bluetooth, I2S, etc.)

-Be familiar with EDA tool Cadence or Mentor




Job Title : EDA Engineer

Location : Chengdu

Target Candidate: Experience in Unix (Linux) and Windows operating systems administration,License management/flexlm

Minimum Experience: 5+ years

Key Areas of Responsibilities:

-Interface with Engineering teams, Design Automation (DA) flow developers and IT organization to

-set up appropriate DA-Infrastructure foundation

-Create, maintain and deploy solutions supporting design foundation to gain in quality and productivity

Required Skills and Attributes

-Programming skills in Perl, Shells, TCL, Python and Cadence SKILL

-Experience with Cadence, Synopsys, Mentor and other design tools




Job Title: Physical Verification Engineer

Location : Shanghai

Target Candidate:  Experience with Physical Verification

Minimum Experience: 3+ years

Key Areas of Responsibilities:

-Develop verification decks including drc, lvs, pex, erc, esd, lup, antenna, dummy fills, dfm etc

-Conduct decks QA and automation for release into internal design environment

-Maintain physical verification and extraction rules decks per foundry updates and bug fixes

Required Skills and Attributes

-Expertise in PVS/QRC, Calibre/XRC code development or with other equivalent tools

-Excellent software skills in TCL and Perl programming

-Power user of Cadence Virtuoso physical layout tools and Skill codes




内推邮箱:

Danbo.Deng@conexant.com

发表于 2016-12-20 16:24:22 | 显示全部楼层
十年前的东家,活过来了并且活得很好,都有模拟设计了。祝福。
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