关于verilog testbench中将多个结果写到txt文件会覆盖的问题

xcxfly

大家好！写了一段testbench，想把每次得到的结果输出到同一个文件中，但是发现最后的值覆盖了前面的几个，代码如下：

1. always @(rxd or txd)
   
2. begin
   
3. write_out_file = $fopen("write_out_file.txt","w");
   
4. #1200;
   
5. if(txd===rxd)
   
6. begin
   
7. $fdisplay(write_out_file,"\n **** time=%t ****",$time);
   
8. $fdisplay(write_out_file,"OK! txd=%d,rxd=%d",txd,rxd);
   
9. end
   
10. else
    
11. begin
    
12. $fdisplay(write_out_file,"\n **** time=%t ****",$time);
    
13. $fdisplay(write_out_file,"ERROR! txd != rxd" );
    
14. $fdisplay(write_out_file,"ERROR! txd=%d, rxd=%d",txd,rxd);
    
15. end
    
16. $fclose(write_out_file);
    
17. end
    

复制代码

想不到解决办法，求助啊，谢谢大家！

杰克淡定

跑完一个case后，mv write_out_file.txt write_out_file_xxx.txt 再去跑下一个。不然连续跑肯定是覆盖

harry_hust

回复 1# xcxfly


   $fopen里面不是有选项么，"w"/"r"/"a"，你看看有啥区别。

xcxfly

回复 3# harry_hust


   好的，谢谢你~