【AMD】热招 ASIC Design & Verification Engineer (FCH)

RecruiterAMD

AMD研发中心招聘ASIC Design & Verification Engineer (FCH)

[url=mailto:请感兴趣的候选人把简历以附件形式发送到maggie1.zhang@amd.com]请感兴趣的候选人以“姓名-应聘职位”的格式把简历以附件形式发送到[/url]Nina.Zhang@amd.com ,请在正文称述应聘理由与优势。

Location：北京市海淀区科学院南路2号融科资讯中心C座北楼19层

Beijing-ASIC Design Engineer (FCH)

Requirements:

The candidate is preferred to be MSEE. The candidate should have good understanding on ASIC/SOC design flow and must be proficient in two or more of the following skill sets:

It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.

The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.

Responsibility:

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, etc.

Beijing-ASIC Verification Engineer (FCH)

Requirements:

The candidate is preferred to be MSEE. The candidate should have good understanding on ASIC/SOC design flow and must be proficient in two or more of the following skill sets:

It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.

Experience with OVM/UVM, C/C++ experience is preferred; Master at least one script language The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.

Responsibility:

The successful candidate will work with team members and apply his/her techniques to work on different phases of complex logic verification for ASIC/SOC project. The role will include working on the following tasks from time to time: verification plan development, verification environment build, test sequence writing and debugging, coverage collection and analysis, etc.