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- module divison(clk,rst_n,start);
-
- input clk,rst_n,start;
- input [7:0] dividend; //被除数
- input [7:0] divisor; //除数
- output done;
- output [7:0] qutient;
- output [7:0] reminder;
- output [15:0] sq_diff;
- output [15:0] sq_temp;
-
-
- reg [3:0] i;
- reg [8:0] s;
- reg [15:0] temp;
- reg [15:0] diff;
- reg isneg;
- reg isdone;
-
- always @(posedge clk or negedge rst_n)
- begin
- if (!rst_n)
- begin
- i <= 4'd0;
- s <= 9'd0;
- temp <= 16'd0;
- diff <= 16'd0;
- isneg <= 1'b0;
- isdone <=1'b0;
- end
-
- else if(start)
- case(i)
- 0:
- begin
- isneg <= dividend[7]^divisor[7];
- s <= divisor[7] ? {1'b1, divisor}:{1'b1,~divisor+1b'1};
- temp <= dividend[7] ? {8'd0,~dividend+1'b1}:{8'd0,dividend};
- diff <= 16'd0;
- i <= i + 1'b1;
- end
- 1,2,3,4,5,6,7,8:
- begin
- diff = temp + {s,7'd0};
- if(diff[15])
- temp <= {temp[14:0],1'b0};
- else
- begin
- temp <={diff[14:0],1'b1};
- i <= i +1'b1;
- end
- end
- 9:
- begin
- isdone <= 1'b1;
- i <= i +1'b1;
- end
- 10:
- begin
- isdone <=1'b0;
- i <= 2'b0;
- end
- endcase
-
- assign done = isdone;
- assign qutient = isneg ? (~temp[7:0]+1'b1):temp[7:0]; //商
- assign reminder = temp[15:8]; //余数
- assign sq_diff = diff;
- assign sq_temp = temp;
- end
- endmodule
-
复制代码
编译之后出现这样的错误:
Error (10170): Verilog HDL syntax error at divison.v(9) near text Â
Error (10170): Verilog HDL syntax error at divison.v(9) near text "Â"; expecting "endmodule"
Error (10170): Verilog HDL syntax error at divison.v(10) near text Â
Error (10170): Verilog HDL syntax error at divison.v(11) near text Â
Error (10170): Verilog HDL syntax error at divison.v(21) near text Â
Error (10170): Verilog HDL syntax error at divison.v(21) near text "Â"; expecting "@", or an identifier
Error (10170): Verilog HDL syntax error at divison.v(22) near text Â
Error (10170): Verilog HDL syntax error at divison.v(23) near text Â
Error (10170): Verilog HDL syntax error at divison.v(24) near text Â
Error (10170): Verilog HDL syntax error at divison.v(25) near text Â
Error (10170): Verilog HDL syntax error at divison.v(26) near text Â
Error (10170): Verilog HDL syntax error at divison.v(27) near text Â
Error (10170): Verilog HDL syntax error at divison.v(28) near text Â
Error (10170): Verilog HDL syntax error at divison.v(29) near text Â
Error (10170): Verilog HDL syntax error at divison.v(38) near text Â
Error (10170): Verilog HDL syntax error at divison.v(39) near text Â
Error (10170): Verilog HDL syntax error at divison.v(40) near text Â
Error (10170): Verilog HDL syntax error at divison.v(41) near text Â
Error (10170): Verilog HDL syntax error at divison.v(42) near text Â
Info (12021): Found 0 design units, including 0 entities, in source file divison.v
不知道怎么办。谢谢 |
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