带PAD的设计出现错误，问：是否MW library错误？跪求解决办法，急！！！！

1027199631

RTL中 进行实例化：

pc3d01 CS(.PAD(csn),.CIN(net_csn));

inv0d0 inv (.I(net_en),.ZN(net_EN));en 为输出使能端，inv0d0为MW库IC035os142中的单元。从下面的结果可以看出，反相器调用无错

pc3t01 OUT (.I(net_out),.OEN(net_EN),.PAD(out));其中pc3t01为三态输出型PAD，pt3d01为输入型PAD，其均为MW库IC035io122_3l中的PAD

icc_shell> check_library   部分结果如下：

Number of cells with missing or mismatched pins in libraries:   176

Error: missing data found. Please refer to LIBCHK-212.  (LIBCHK-101)

Warning: List of pins missing in logic library (LIBCHK-212)

------------------------------------------------------------------------------

Physical library           Cell name             Pin name    Pin direction

------------------------------------------------------------------------------

IC035io122_3l              pc3d01                VSSQ        

IC035io122_3l              pc3d01                VSSQ        

Error: List of pins mismatched in logic and physical libraries (LIBCHK-213)

Logic library:    IC035io122_max

Physical library: /home/ICC/mw_lib/IC035io122_3l

-----------------------------------------------------------------------------------

                                          Pin direction           Pin type

Cell name                    Pin name    Logic   Physical     Logic         Physical

-----------------------------------------------------------------------------------

pc3t01                       VDD         unknown             primary power  signal

pc3d01                       VDD         unknown             primary power  signal

icc_shell> check_tlu_plus_files   结果如下：

Information: linking reference library : /home/ICC/mw_lib/IC035io122_3l. (PSYN-878)

Information: linking reference library : /home//ICC/mw_lib/IC035os142. (PSYN-878)

  Linking design 'TOP'

  Using the following designs and libraries:

  --------------------------------------------------------------------------

  * (7 designs)               TOP.CEL, etc

  IC035os142_max (library)    /home/ICC/db/IC035os142_max.db

  IC035os142_min (library)    /home/ICC/db/IC035os142_min.db

  IC035io122_max (library)    /home/ICC/db/IC035io122_max.db

  IC035io122_min (library)    /home/ICC/db/IC035io122_min.db

Error: Can't find input port 'VSSO' on reference to 'pc3t01' in 'TOP'. (LINK-1)

Warning: Unable to resolve reference 'pc3t01' in 'TOP'. (LINK-5)

Error: Can't find input port 'VSSO' on reference to 'pc3d01' in 'TOP'. (LINK-1)

Warning: Unable to resolve reference 'pc3d01' in 'TOP'. (LINK-5)

Error: Can't find input port 'VSSO' on reference to 'pc3d01' in 'TOP'. (LINK-1)

Warning: Unable to resolve reference 'pc3d01' in 'TOP'. (LINK-5)

Error: Can't find input port 'VSSO' on reference to 'pc3d01' in 'TOP'. (LINK-1)

Warning: Unable to resolve reference 'pc3d01' in 'TOP'. (LINK-5)

Load global CTS reference options from NID to stack

# GUI Debug: Building dc from empty. -- Time: 1sec 318ms

Sanity check for TLU+ vs MW-Tech files:

max_tlu+: /home/ICC/tluplus/CSMC6S035DPTM_M3524_tran_max.TLUPlus

min_tlu+: /home/ICC/tluplus/CSMC6S035DPTM_M3524_tran_min.TLUPlus

mapping_file: /home/ICC/tluplus/CSMC035DPTMPCMM.map

max_emul_tlu+: **NONE**

min_emul_tlu+: **NONE**

MW design lib: xx

--------- Sanity Check on TLUPlus Files -------------

1. Checking the conducting layer names in ITF and mapping file ...

[ Passed! ]

2. Checking the via layer names in ITF and mapping file ...

[ Passed! ]

3. Checking the consistency of Min Width and Min Spacing between MW-tech and ITF ...

[ Passed! ]

----------------- Check Ends ------------------

在进行pg连接时，derive_pg.tcl脚本文件如下：

derive_pg_connection -power_net VDD -power_pin VDD -ground_net VSS -ground_pin VSS

derive_pg_connection  -power_net VDDO -power_pin VDDO -ground_net VSSO -ground_pin VSSO

derive_pg_connection  -power_net VDDQ -power_pin VDDQ -ground_net VSSQ -ground_pin VSSQ

derive_pg_connection -power_net VDD -ground_net VSS –tie

执行结果如下：

icc_shell> source scripts/derive_pg.tcl

begin derive_pg_connection...

--- connected 1081 power ports and 1081 ground ports

Information: PG PORT PUNCHING: Number of ports connected:                2162 (MW-337)

Information: PG PORT PUNCHING: Total number of changes:                  2162 (MW-339)

begin derive_pg_connection...

Error: Pin name VDDO specified by power_pin or ground_pin option is invalid. (MWUI-715)

Error: Pin name VSSO specified by power_pin or ground_pin option is invalid. (MWUI-715)

derive pg failed

begin derive_pg_connection...

Error: Pin name VDDQ specified by power_pin or ground_pin option is invalid. (MWUI-715)

Error: Pin name VSSQ specified by power_pin or ground_pin option is invalid. (MWUI-715)

derive pg failed

begin derive_pg_connection...

-- reconnected total 1 tie highs and 8 tie lows

Information: PG PORT PUNCHING: Number of ports connected:                1 (MW-337)

Information: PG PORT PUNCHING: Total number of changes:                  1 (MW-339)

分特

ref lib里的pg pin类型不对。
milkyway里跑 dbDumpGPortTable "IC035io122_3l" "IC035io122_3l.gport.dump"，把vdd vss vsso这些pin纠正过来，改成inout power/ground，再load回去

1027199631

回复 2# 分特


   我试试，多谢多谢

1027199631

回复 2# 分特
大神，您好！根据您的建议，已跑Milkyway，部分结果如：

dbSetCellPortTypes "IC035io122_3l" "pc3d01" '(

  ("CIN" "Output" )

  ("PAD" "Input" )

) #f

dbSetCellPortTypes "IC035io122_3l" "pc3t01" '(

  ("I" "Input" )

  ("OEN" "Input" "TristateDisable" )

  ("PAD" "Output" "Tristate" )

) #f

pc3d01、pc3t01并未显示VDD/VSS、VDDO/VSSO、VDDQ/VSSQ 端口，请问：我该如何修改？在哪修改？修改之后该怎样load回去？

求大神解答，感激不尽

黄zhuoquan

我也遇到过check_library出现类似的问题，不知道用什么来修改工艺库文件？

1027199631

回复 5# 黄zhuoquan


   还未解决呢

1027199631

回复 2# 分特

ref_lib的问题已解决

黄zhuoquan

回复 7# 1027199631

怎么解决的？

abao123

回复 4# 1027199631
dbSetCellPortTypes "LIB" "CELL" '(
  ("VDD" "Inout" "Power" )
  ("VSS" "Inout" "Ground" )
) #f

jiazhang

回复 7# 1027199631

请问楼主 是如何解决的呢？