VCS 编译时出现问题（求解！急，在线等）

1027199631 · 发表于 2016-3-24 14:42:28

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使用指令 vcs slave_test.v -y ./rtl +libext+.v 进行编译，结果如下：

Chronologic VCS (TM)

Version C-2009.06 -- Thu Mar 24 14:26:55 2016

This program is proprietary and confidential information of Synopsys Inc.

and may be used and disclosed only as authorized in a license agreement

controlling such use and disclosure.

Parsing design file 'slave_test.v'

Parsing library directory file './rtl/SPI_S.v'

Parsing library directory file './rtl/Reset_Synchronizer.v'

Parsing library directory file './rtl/spi_slave.v'

Parsing library directory file './rtl/sync_detect.v'

Parsing library directory file './rtl/reset_DRDY.v'

Parsing library directory file './rtl/reset_sck.v'

Top Level Modules:

slave_test

TimeScale is 10 ns / 1 ps

Starting vcs inline pass...

1 module and 0 UDP read.

recompiling module slave_test because:

Some compilation options have been changed.

if [ -x ../simv ]; then chmod -x ../simv; fi

g++ -o ../simv -melf_i386 -m32 5NrI_d.o 5NrIB_d.o V6Uy_1_d.o rmapats_mop.o rmapats.o SIM_l.o /home/EDA/tools/VCS2009/linux/lib/libvirsim.a /home/EDA/tools/VCS2009/linux/lib/librterrorinf.so /home/EDA/tools/VCS2009/linux/lib/libsnpsmalloc.so /home/EDA/tools/VCS2009/linux/lib/libvcsnew.so /home/EDA/tools/VCS2009/linux/lib/vcs_save_restore_new.o /home/EDA/tools/VCS2009/linux/lib/ctype-stubs_32.a -ldl -lc -lm -lpthread -ldl

/usr/bin/ld: crt1.o: No such file: No such file or directory

collect2: ld returned 1 exit status

make: *** [product_timestamp] Error 1

Make exited with status 2

CPU time: .129 seconds to compile + .005 seconds to elab + .017 seconds to link