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芯片精品文章合集(500篇!)    创芯人才网--重磅上线啦!
楼主: sunny555

[招聘] 招聘 芯原微电子成都招聘信息

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 楼主| 发表于 2016-4-13 16:29:22 | 显示全部楼层
回复 10# hongkong2


   收到,谢谢,请你耐心等候。
 楼主| 发表于 2016-4-13 16:39:25 | 显示全部楼层

l
现公司新增一个职位,信息如下,欢迎大家关注哟

  
Senior Complier Engineer
  
Job Requirements
1.Compiler maintenance and enhancements for arange of DSP cores
2.Work on scheduler and optimizer for improvingperformance and code density of compiler generated code
3.Assist in porting of GNU compiler sources
4.Work with Application developers and Hardwareengineers to debug code generation bugs and identify any code generationdeficiencies or optimization opportunities
5.Work with a distributed team  inbuilding and verifying the entire tool chain
6.Assist field engineers in supporting customerswith tools issues
  
Required skills and knowledge
1.Self motivated and able to work with littlesupervision, Team player
2.Innovative and passionate about coding andexcited to take on challenging assignments
3.Expert in C/C++ programming with ability tolearn and master new C projects with minimal support
4.Good understanding of processor architecture andinstruction set
5.Comfortable with Linux and Windows environments
6.Good Perl skills
7.Good written and spoken English
8.Experience working  with GNU C/C++ orany other compiler sources
9.Comfortable working with whole tool chainincluding assembler, linker, debugger
10.Education : BS/MS/PhD in Computer Science/Mathwith 5+ years experience in embedded software


发表于 2016-4-16 23:25:16 | 显示全部楼层
回复 11# sunny555

请问,是有查到我的面试安排? 请问是安排在什么时间呀?谢谢
 楼主| 发表于 2016-5-11 15:27:26 | 显示全部楼层
现公司再新增一个职位,具体信息如下,欢迎大家的关注哦!

Senior ASIC Verification Engineer
  
Job Requirements
1. Develop environments for complex system functional verification.
2. Create and maintain RTL integration of system level components.
3. Write verification plans for system level IPs and systems.
4. Develop verification environments for IP and systems using C, verilog, Specman, SystemVerilog, etc.
5. Contribute improvements to verification methodologies, and toolsets.
6. Develop RTL designs from specifications.
  
Required skills and knowledge:
1. 3-8 years working experience
2. BS/MS/PhD in Electrical/Computer Engineering
3. Strong coding skills - using languages: Verilog, SystemVerilog, Perl, assembly, C++, C, Linux
4. Great debugging and problem isolation skills.
5. AXI, AHB, APB interconnect
6. Computer architecture, memory subsystems.
7. Implementing verification methodologies including constrained random verification, coverage closure, Assertion Based Verification, Universal Verification Methodology,
8. Implementing RTL logic designs.

快快加入“芯”家吧,we are family!!!!!  
 楼主| 发表于 2016-5-17 14:01:56 | 显示全部楼层
欢迎大家投递简历哦,中英文简历都需要,投递邮箱:yujuan.li@verisilicon.com.

芯原微电子(成都)有限公司诚邀您的加入!!!
发表于 2016-5-20 20:50:07 | 显示全部楼层
你好!请问需要版图工程师吗?
 楼主| 发表于 2016-5-24 10:05:56 | 显示全部楼层
回复 16# chen1q


   你好,目前没有招聘这个职位哦,谢谢你对芯原成都公司的关注,也请你继续关注我们公司哦。
 楼主| 发表于 2016-5-24 10:06:47 | 显示全部楼层
有没有做 DV,ASIC Verification,Senior Complier Engineer 和Video IP design 的大神呀,投点简历过来呗,推荐也可以。
 楼主| 发表于 2016-6-2 16:46:11 | 显示全部楼层
说好的人呢?都到哪儿去了???{:3_55:}{:3_55:}
发表于 2016-6-4 15:25:44 | 显示全部楼层
@sunny555   video ip 一定要5年啊,只有两年呢
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