vcs仿真 -cm的问题请教

hao_0071

命令行是：vcs test.src top.v -l comp.log -cm_glitch 1

结果出现以下提示，不认-cm，请各位帮忙看下是什么原因引起。simv文件能产生，也能运行，也有结果。
Warning-[VCM-INSOPTMIS] Coverage instrumentation option missing
  Design is not compiled with 'any -cm' option. No compile-time
  instrumentation is done for any metric of code coverage in the design.
  The sub-options given with 'any -cm_*' switch will not work. Either include
  the '-cm line/tgl/fsm/cond/line/path/assert' option or remove sub-options.

hao_0071

呼唤高手！！