[code]module cfcard (
//---system signals---
input clk,
//input rst,
//---control signals---
//input wrreq,
//input rdreq,
//input[27:0] LBAADR,
//input[7:0] dat_in,
output reg wren,
output reg rden,
output [7:0] dat_out,
output reg dat_valid,
//---cfcard signals---
input CF_WAIT,
input CF_READY,
output reg CF_OE,
output reg CF_WE,
output reg[1:0] CF_CE,
output reg[10:0] cfadr,
output reg CF_REG,
inout [15:0] cfdat
);
///////////////////////////////////////////////////////////
reg rst;
reg [31:0] rst_count='d0;
always@(posedge clk )
begin
if(!rst_count[27]) |