|  | 
 
| 
modelsim仿真xfab工艺的综合后网表文件,提示的错误是:
×
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册  # ** Error: (vsim-3033) E:/verilog_design/digital_chip_v2.0/spi_v1.7/verilog_netlist/D_CELLS.v(25630): Instantiation of 'u_mx2' failed. The design unit was not found.
 #         Region: /tb_spi_top/full_chip_u/spi_top_u/U1775
 #         Searched libraries:
 #             E:\verilog_design\digital_chip_v2.0\spi_v1.7\work
 
 
 
 D_CELLS.V的25630行是一个MU2IX0单元里面例化的另一个小单元u_mx2:
 
 module MU2IX0 (IN0, IN1, Q, S);
 
 input     IN0, IN1, S;
 output    Q;
 
 // Function Q: !((!S*IN0)+(S*IN1))
 u_mx2     i5  (n_3, IN0, IN1, S);                         ////////25630行
 not       i4  (Q, n_3);
 
 // timing section:
 specify
 
 (posedge S => (Q +: Q)) = (0.02, 0.02);
 (negedge S => (Q +: Q)) = (0.02, 0.02);
 if ((IN0 == 1'b0 && IN1 == 1'b1)) (S -=> Q) = (0.02, 0.02);
 (IN0 -=> Q) = (0.02, 0.02);
 (IN1 -=> Q) = (0.02, 0.02);
 
 endspecify
 endmodule
 
 
 请高手指点,谢谢啦~
 file:///C:\Users\WM\AppData\Roaming\Tencent\Users\869086055\QQ\WinTemp\RichOle\(_(V{PICLUTE{BR3U@~}PJA.png
 | 
 |