Job Description/Qualifications:
Responsibilities:
- IP module integration in fullchip level
- RTL quality checks and flow enhancement
- Padring Design and verification
- Tree infrastructure maintenance and flow enhancement
- Project management by communicate with chip manager and unit leads
Minimum Requirements:
- BS / MS in electronics / computer science and related.
- Above 2 years of ASIC design experience
- Strong perl script knowledge
- Familiar with all aspects of the frontend ASIC design
- In-depth knowledge on synthesis and DFT (scan chain, ieee1500 etc)
- Excellent analytical and problem solving skills
- Broad knowledge with SOC architecture and Computer architecture is a big plus.
- Fluent English (both written and spoken) and excellent communication skills
- Good team work spirit, easy to cooperate with team members
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2016-1-15 17:31:15
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