PT中执行以下命令: |
set search_path "../ref/" |
set link_path "* max.db" |
read_verilog ../SPI_PCM.v |
current_design SPI_PCM |
link_design |
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出现以下问题 |
Loading db file '../ref/max.db' |
Linking design SPI_PCM… |
Warning:Unable to resolve reference to 'SERIALSLAVE' in 'SPI_PCM'.(LINK-005) |
Warning:Unable to resolve reference to 'TESTOUTSEL' in 'SPI_PCM'.(LINK-005) |
Warning:Unable to resolve reference to 'PCM' in 'SPI_PCM'.(LINK-005) |
…… |
Information:Creating black box for U1/SERIALSLAVE…(LINK-043) |
Information:Creating black box for U2/TESTOUTSEL…(LINK-043) |
Information:Creating black box for U3/PCM…(LINK-043) |
…… |
Information:251(88.3%) library cells are unused in library max.db…… |
|
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推测是
SPI_PCM中的stdcell link没问题,但SPI_PCM中子module(SERIALSLAVE,PCM等)link有问题, |
把它们认成了black box。 |
请问各位有什么解决办法? |