Cadence上海和北京2015年12月IPG部门热招职位

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Cadence上海和北京2015年12月IPG部门热招职位如下：

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1. Lead/Senior Verification Engineer (Location: SH)

Position Description:
 Deliver/implement advanced verification solutions by utilizing Cadence’s IncisiveVerification product portfolio. The engineer should be able to act as a strong teammember and contributor, leading team projects and initiatives. Exercise judgmentwithin generally defined practices and policies.
 Specific duties include:
 Deep understanding on ASIC design and verification flow
 Excellent knowledge of advanced verification methodology likeeRM/OVM/UVM/VMM
 Familiar with Cadence’s Incisive Plan to Closure Methodology (IPCM)
 Proficiency in System Verilog, System C and/or e (Specman)
 Developing and using Verification Components (eVC, OVC,UVC,VIP)
 Developing and using assertion based verification and formal analysis methods
 Skilled in scripting language, such as Perl, C shell, Python, Make file
 Assessing the project verification requirements
Position Requirements:
 BS degree with 4+ years of applicable experience, MS degree with 2+ years ofapplicable experience in electrical engineering, microelectronics, comparableengineering science or solid state physics.
 Essential that the individual demonstrates strong communication, verbal and written.Requires good communication skills in English.
 Will have demonstrated hands-on experience and expertise with Cadence verificationdesign tools or equivalent tools, flows and methodologies required to execute averification project.
 Will have demonstrated successful completion of 3+ verification projects as anindividual contributor
 Will have DDR project verification experience

2. Lead/Senior Physical Design Engineer (Location: SH)

Position Description:
 Focus on high speed digital DDR and HBM IP physical implementation
 Have good physical design experiences in the digital implementation domainincluding Floorplan, P&R, Physical verification, DFM.
 Have a solid background in circuits, electronics & physics & should be very willing tolearn new technology for advance node and design methodology
 Skilled in scripting language, such as Perl, C shell, Make file
 Feeling responsible for technical delivery, good team played, design quality/schedulefocus
Position Requirements:
 Essential Qualifications: Have MS degree with 2 ~4+ years of applicable experience,MS degree with 4 ~ 6+years of applicable experience in electrical engineering,microelectronics.
 Essential that the individual demonstrates strong communication skill
 Requires good communication skills in English.

3. Lead/Senior Front-end Design Engineer (Location: SH/BJ)

Position Description:
 Deliver/implement DDR/HBM IP. The engineer should be able to act as a strong teammember and contributor. Exercise judgment within generally defined practices andpolicies.
Specific duties include:
 Proficiency in logic design, simulation, synthesis, STA and testing
 Proficiency in Verilog and its simulation environment
 Good knowledge of IC design
 At least two years’ experience driving complex IC development projects, excellentcommunication skills and the uncanny ability to both lead and contribute in acooperative team environment.
Position Requirements:
 Essential Qualifications: Must have BS degree with 4+ years of applicable experience,MS degree with 2+ years of applicable experience in electrical engineering,microelectronics, comparable engineering science or solid state physics.
 Essential that the individual demonstrates strong communication, verbal and written.
 Requires good communication skills in English.
 Will have demonstrated successful completion of 5+ design projects as an individualcontributor
 Familiar with JEDEC-DDR/HBM, DFI and AMBA protocols and have DDR projectdesign experience

4. Senior Program Manager (Location: SH)


Position Description:
 We are looking for a Senior Program Manager who will be responsible for the overallcoordination of Key Customer Engagements and R&D Development Projects withinthe Design IP Group. The candidate must have experience in IP and/or SoC Designand a history in successfully program managing complex IP/SoC Programs with endcustomers. A PMP Certification or equivalent is desirable.
Main Job Tasks and Responsibilities
 lead the planning and track the implementation of project
 facilitate the definition of project scope, goals and deliverables
 define project tasks and resource requirements
 develop full scale project plans
 manage/track project resource allocation
 plan and schedule project timelines
 track project deliverables using appropriate tools
 provide direction and support to project team
 support quality assurance
 constantly monitor and report on progress of the project to all stakeholders
 present reports defining project progress, problems and solutions
 implement and manage project changes and interventions to achieve project outputs
 manage customer engagement – project and relationship management
 collaborate with Sales, Marketing, Finance and Engineering to assure effective andefficient project execution
Position Requirements:
Education and Experience
 knowledge of both theoretical and practical aspects of project management
 knowledge of project management techniques and tools
 direct work experience in project management capacity
 proven experience in people management
 proven experience in strategic planning
 proven experience in risk management
 proven experience in change management
 proficient in project management software
 min 7+ years verifiable successes managing SoC/IP deliverables
 BSEE at a min. MSEE & MBA preferred
Key competencies
 critical thinking and problem solving skills
 planning and organizing
 decision-making
 communication skills
 influencing and leading
 team work
 conflict management
 adaptability

5. Principal Deployment / Solution Engineer (Location: SH)

Position Description:
 The Deployment Engineer is expected to be an expert in a specific domain ofVerification IP family – protocol and product wise.
 Our main role is to be Sales acceleration for top Cadence accounts and enable presales technical activities and product adoptions. To ensure that, we must beverification expert and understand customer design and verification flow.
 As a solution engineer we must be able to translating high level requirement thatcoming from customers to technical spec and define a solution that fits to customerneeds.
 The Deployment / Solution Engineer is expected to work both independently and incollaboration with other team members ( RnD, Marketing, support) to ensure alldimension of the product are align .
 This role require some travels to customer sites.
Position Requirements:
 BSc with Electrical engineering or Computer Science
 At least 5 years of experience with Verification and Design
 Experience with Developing Verification environments using System Verilog or Specman /e
 Familiar with the UVM methodology
 Familiar with standard protocol like AMBA/ MIPI/ USB/ PCIE
 Experience with Unix / Linux environment
 Very good English knowledge, capable to have fluent discussions and communicateFace to Face and through emails
 Team orientation, mature work attitude, and good judgment under pressure
 Customer service approach

6. Lead Design engineer-STA (Location: SH/BJ)

Position Description:
 In charge of IP and SOC logic design, and Implementation (focus on STA).
 Daily duties include: Digital IC micro-architecture, RTL coding, Logic Synthesis,Function Verification, DFT, and Static Timing Analysis.
 HDL language Knowledge, like verilog or vhdl is necessary.
 C/C++/perl/tcl/csh/python, UNIX, Linux experience are plus.
 Excellent analytical and problem-solving skills. Quick learner-able to learn and applytechnical and complex topics.
 Excellent communication skills and the uncanny ability in a cooperative teamenvironment are required.
 Self-motivated, result-oriented, can take ownership and follow-through on tasks.
Position Requirements:
 Master degree or above (2-5 year working experience)
 Major in Micro-electronics, Electronic Engineering, Computer Science, InformationTechnology or equivalent
 Ability to work effectively alone or as well as in the team.
 Essential that the individual demonstrates strong communication, verbal and written
 Requires good communication skills in English.
 Good at any following skill sets: ASIC design, FPGA design, Computer architecture,SOC design based on ARM/MIPS.
 Experience of DDR

7. Principal Design Engineer

Position Description:
 Cadence/Tensilica is a leading provider of configurable embedded processortechnology and DSPs for various markets. As a member of the DSP engineeringgroup you will be responsible for verification of advanced DSP cores and theirinstruction set architectures and hardware implementations. You will implementarchitectural simulation test benches in C/C++/RTL, write C/assembly languagediagnostics, assertion checkers or coverage monitors to meet target verificationgoals. You will also assist with developing test plans, debugging failures andanalyzing coverage information. You will work closely with the market-specific DSPteams, Design Verification, and RTL and EDA teams.
Position Requirements:
 Knowledge of DSPs, instructions sets, computer arithmetic concepts, and processorarchitecture concepts
 Good knowledge of C (C++ will be a plus)
 Working knowledge of Verilog and popular EDA simulators and testbenchmethodologies
 Knowledge of scripting languages such as Makefile/Perl is desired
 Knowledge of assembly programming and programming in a high level languagesuch as C
 Good English communication skills – both written and verbal
 Strong problem solving skills along with an ability to work independently and incooperation with global teams
 MS degree in EE/CS with 3 to 5 years industry experience required.

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