福利到了。。公司每个季度都在赚钱。。。福利待遇都不错。。。不信网上查查看

TianBian365

有兴趣发往我的邮箱tianbian365@hotmail.com, 走内部推荐概率高，我也可以拿到推荐礼包，到时候和你一起吃掉他。。。

公司名称是 豪威科技 小米啊，华为啊，手机摄像头以及产品国内 TOP1， 国际TOP2

Analog Design Engineer

Position Overview:

As an Analog IC Design Engineer you will perform analog and mixed signal design, characterization and evaluation of analog circuitry for PMU's, ADC/DAC's, and other base band analog circuits

Responsibilities:

1. Design PMU, AD/DA, and other base band analog IC circuit.

2. Use EDA tool to run simulation and function verification.

3. Design and optimize chip layout

4. Guide layout engineer to optimize layout

5. Chip test and debug

Requirements:

1. MSEE with major in semiconductor or microelectronis;

2. Experience in Cadence EDA tools;

3. Team player with good communication skills

4. Minimum 5 years experience in mixed signal circuit design

5. Demonstrate good knowledge and experience in advanced analog and mixed-signal circuit design, experience in one or more of the following circuits, is a plus:

- Audio CODEC；

- SAR ADC

- Pipeline ADC；

- DC-DC converter

- Bias, Bandgap, Voltage Regulators

Layout Design Engineer

Position Overview:　

Responsible for IC full-custom analog layout, verification of the layout (DRC/ERC/LVS), RC extraction for post simulation

Responsibilities:　

Primary (70%):

1. Full custom analog layout/verification and RC extraction.

2. Perform block level layout. Conduct physical verification (DRC and LVS using Cadence tools).

Secondary (30%):

1. Team work with analog designers, optimize layout.

2. Perform floor planning and placements (pad locations and custom routing).

Requirements:　

1. Bachelor or above degree with 5 years experiences in CMOS IC full-custom layout.

2. Experiences in Mixed signal/analog/high speed layout.

3. Familliar with layout skills and knowledge is must.

4. Good teamwork/communication/positive is must.

5. Familiar with Cadence IC layout and verification tools

6. Having massive IP block experience

Plus:

1. Familiar with 0.18/0.13/0.09/0.065/0.04 um CMOS process and design rule is a plus.

2. Familiar with ESD/Latch up/antenna and related layout solutions is a plus.

3. Familiar with layout size reduction is a plus, with standard cell experience is good.

4. Familiar with rule deck is a plus.

RFIC Design Engineer

Position Overview:

RFIC block and top level circuit specification, design and layout, test and debug

Responsibilities:

1. Perform low cost/low power RF circuit design and simulation for wirelss product

2. Do or guide layout engineer to do RF circuit layout, and performance post-layout simulation

3. Engineering test and debug for block circuit and chip product

4. Documentation of RFIC specification, design and test report

5. Mentor of junior RFIC designers

Requirements:

1. Master or above degree in EE or seminconductor area

2. Minimum 2 years experience in RFIC circuit design

3. Good knowledge of RF transceiver system

4. Direct WiFi/Bluetooth product experiences are preferred

5. Good at EDA and simulation tools, such as ADS/Matlab/Cadence etc.

6. Good people communication skill and team work

Sr. Mixed-Signal Design Engineer

We are looking for a mixed-signal design engineer or architect to lead the development of high-speed serial and parallel I/O, digital designs of from PHY to upper layers, and clock generation / distribution for CMOS image sensor and bridge chip products. The candidate should have a proven record of defining the architecture and designing complex ICs in state of the art CMOS process technologies and has successfully placed products into volume production, preferably multiple times.

Skills:

1. Creative thinking to solve problems demanding higher performance, lower power and small chip size

2. Both analog and digital design background preferred.

3. Familiar with high speed interface functions and electrical specs such as DDR-3/LP-DDR2 PHY, USB, HDMI, Ethernet et al.

4. Strong communication, presentation and debug/problem solving skills

5. Ability to work independently as well as in teams and across functions and levels

Experience:

1. Minimum: Masters degree in Electrical Engineering with 5+ years experience.

2. Design spec and architecture definition.

3. Direct design experience in products with highspeed interfaces.

4. Deep sub-micron process design experience at 90nm/65nm/40nm or more advanced nodes.

5. A track record of developing high volume commercial products

6. Working knowledge of industry best practices.

ASIC Design Engineer

Position Overview:　

The candidate will join a team of highly competent ASIC designers involved in design, verification, and implementation (ASIC) of advanced platform for OmniVision's future generation multi-media products.

Responsibilities:　

Primary (70%):

1. Provide detailed block-level design and documents;

2. Develop and execute thorough block level simulation and lab verification plan;

3. Participate in the FPGA platform development and lab debugging.

Secondary (30%):

1. Participate in block level architecture design;

2. Assisting embedded FW development.

Requirements:　

Experience/Skills:

1. MSEE/CE with 1+ years of industry experience

2. Strong analytical, and problem solving skills as well as hands-on lab debugging skills

3. Good knowledge of RTL simulation and synthesis. Knowledge of design for low power and design for manufacturing

4. Able to write C/C++ code to model RTL blocks for simulation and verification.

5. Able to write reusable Verilog RTL codes, follow design and DFT guidelines.

6. Able to write verification test plans, and be able to run synthesis, static timing analysis, formal verification.

7. Knowledge in languages relevant to the ASIC development process including Verilog, Unix Scripting, Perl, and Tcl.

8. DSP function implementation experience is a plus.

9. Self-motivated, excellent communication skills and ability to excel in a team environment.

feynmancgz

回复 1# TianBian365


   OmniVision在国内原来叫豪威啊

lwjee

DDR-3/LP-DDR2 PHY。买个IP得了

semico_ljj

回复 1# TianBian365


   一般吧

demon0821

工作地点在哪里呢？

hszgl

怎么这个招聘跟安利似的。。。