VHDL乘法器

qianjinliang

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity mul is

port(in1   :  in   std_logic_vector(3 downto 0);

     in2   :  in   std_logic_vector(3 downto 0);

  pout  :  out  std_logic_vector(7 downto 0));
end entity mul;

architecture func of mul is
begin

pout <= in1 * in2;
end architecture func;