AMD MTS Engineer for front-end integration

RecruiterAMD

Location:Shanghai

Responsibility:

•
Integrate functional IPs into SoCper architectural requir

ement.

•
Develop RTL code for macro blocksin Verilog HDL and make

sure functional correct and reusable for differentconfiguration.

•
Participate in makingfunctional/technology based chip tar

gets in timing, area, power. Develop timing constraint,power intent spec acco

rdingly.

•
Synthesis and deliver qualifiednetlist, cowork with PD to

settle chip floorplanand achieve timing closure.

Requirement:

•
Major in EE, CS or related, MasterDegree with 3+ years or

Bachelor with 5+years working experiences in ASIC Company.

•
familiar with one or more ASICflows (logic synthesis, STA

, formality check, Design for Power ) and usage of relatedEDA tools.

•
Familiar with scriptlanguages((tcl, perl etc.) in unix/li

nux.

•
Good written and spoken English.

•
Good communication skills and beable to work both indepen

dently and in a team.

有意者请将简历发送到nina.zhang@amd.com