soc总监或数字经理-芯得20151118

jj_seu

Position: Senior Manager or Director, depending upon qualification, ofSOC Design

简历发 [url=mailtoffer@hi-talent.net]offer@hi-talent.net[/url]

Job Description:

(1)   Lead a SOC design team thatincludes IC architecture, logic design, integration, verification, andvalidation.

(2)   Provide technicalconsultation and resolve technical issues on product development.

(3)   Work with MKT for productdefinition, SE for system design, SW for verification and validation

(4)   Lead tasks related to ICproduction, including issue debugging, bug fix, and solution.

Job Requirement

•     Fluent in Verilog, Familiar with System Verilog and/or System C

•     Familiar with C language. Knowledge of scripting languages is a plus.

•     Intimate knowledge on SOC architecture

•     Familiar with RISC architecture and bus protocols such as AXI and AHB

•     Intimate knowledge on bus arbitration for SOC design

•     Familiar with FPGA prototype verification flow

•     Knowledge of SOC peripheral modules such as flash controller, DDR controller,AV interfaces (HDMI, CVBS, YPbPr, I2S, S/PDIF)

•     Knowledge of audio and video technology

•     Experience on large-scale emulator system (Veloce and/or Palladium)

•     Master degree with at least 10 years of IC development experience

•     Successful IC tape-out in 40 nm or more advanced processes

•     Proven track record of large-scale SOC production

Senior Digital Manager 简历发 [url=mailtoffer@hi-talent.net]offer@hi-talent.net[/url]

Job description:

- Conduct technical feasibilityanalysis,  define chip micron architecture and module spec’s;

- Work with analog design lead for newproduct development project planning and tracking;

- Design, implementation, and verificationof digital in mixed-signal ICs;

- Perform backend digital design (logicsynthesis, formal check, define design constraints for place and route, performtiming closure, DFT)

- Script based synthesis & timinganalysis on GHz working frequency

- Support system, test and product teamwith chip debugging, failure analysis, characterizations and product releaseefforts

Requirements:

- PH.D or MSEE with minimum 10-year designand project lead experience of mixed-signal chip development experience

- Solid knowledge and design experience invery high speed SoC with embedded MPU

- Projects tape out experience with 65nmprocess, 40nm or 28nm

- Relevant experience on DDR/Serdesinterface is a plus

- Solid knowledge of high-speedsynchronous/asynchronous circuit design, family with standard cell architectureand behavior

- Family with low-power-design flow andtechniques

- Strong skills of Verilog RTL coding,verification and debug

- Hands on experience in EDA tools such asCadence NC-Sim, Synopsys DC, PT, etc.

- Solid knowledge of documentation ofdesign report

- Highly organized and self motivated

- Ability to plan and  manage aproject and effectively drive team’s execution

Best Regards

Jane.Jin 金娟

Principal Consultant & General Manager @ Hi-TalentConsulting Co.,Ltd.

上海芯得企业管理咨询有限公司

上海芯相会企业管理咨询有限公司

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