电容大小并”
5)源头进来磁珠当头
6)电感离芯片引脚最近原则
7)GND越完整越好,电容到GND最近原则,可考虑在PAD上打过孔到GND
8)芯片特殊要求:
- 反馈点从最远端返回;
- C1-C5电容最近原则;
-远离电磁转化元件,防止任何变压器耦合
官方layout 应用说明:
1. The power traces consisting of the PGND trace, the SW trace, the PVIN trace, the VIN and GNDA traces, should be kept short direct and wide.
2. Does each of the VFBx pins connect directly to the respective feedback resistors? The resistive dividers
must be connected between the (+) plate of the corresponding output fi lter capacitor (e.g. C2) and GNDA.
If the circuit being powered is at such a distance from
the part where voltage drops along circuit traces are
large, consider a Kelvin connection from the powered
circuit back to the resistive dividers.
3. Keep C1 and C5 as close to the part as possible.
4. Keep the switching nodes (SWx) away from the sensitive VFBx nodes.
5. Keep the ground connected plates of the input and output capacitors as close as possible.
6. Care should be taken to provide enough space between unshielded inductors in order to minimize any transformer coupling