【eBook】SystemVerilog for Design

Zyson

                               
登录/注册后可看大图

http://www.amazon.com/SystemVerilog-Design-Guide-Hardware-Modeling/dp/0387333991/ref=pd_sim_b_2/103-2423481-1392628?ie=UTF8&qid=1180093612&sr=1-9

Book Description

Systemverilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog hdl). These extensions address two major aspects of HDL-based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs.

The first edition of this book addressed the first aspect of the SystemVerilog extensions to Verilog. Important modeling features were presented, such as two-state data types, enumerated types, user-degined types, structures, unions, and interfaces. Emphasis was placed on the proper usage of these enhancements for simulation and synthesis.

SystemVerilog for Design, Second Edition has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes that were made between the first edition of this book was written and the finalization of the new standard. It is important that the book reflect these syntax and semantic changes to the SystemVerilog language.

In addition, the second edition features a new chapter that explanis the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.

answerdou

haoshu,kankan

taiishan

大力支持好东西

wwqqmm

大力支持好东西

LAS.xs

hao!!

luoqc

下载了
顶

zk555

不错不错！！继续努力！

freelion

真的是太感谢了，谢谢

Bobxiaoyong

good book

robberxiong

edaboard上的书。