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Power-Efficient High-Speed Parallel-Sampling ADCs for Broadband Multi-carrier Systems
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您需要 登录 才可以下载或查看,没有账号?注册  Describes a signal/system-aware design approach for ADC design Presents a parallel-sampling architecture to exploit a-priori knowledge of the multi-carrier signal for enhancing power efficiency
 
 Includes two design examples in advanced CMOS technology for broadband multi-carrier systems, with discussions of the tradeoffs at various levels of the design
 
 Presents the IC implementation of an 11b 1GS/s parallel-sampling ADC in CMOS 65nm, showing state-of-the-art power efficiency
 
 
 Introduction
 Enhancing ADC Performance by Exploiting Signal Properties
 Parallel-Sampling ADC Architecture for Multi-carrier Signals
 Implementations of the Parallel-Sampling ADC Architecture
 Conclusions and Recommendations
 
 
 
  Power-Efficient High-Speed Parallel-Sampling ADCs for Broadband Multi-carrier Systems.pdf
            
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