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INFORMATION AND WARNINGS
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1 layout instance was filtered and its pins removed from adjoining nets.
4 layout mos transistors were reduced to 2. 1 connecting net was deleted.
2 mos transistors and 1 connecting net were deleted by split-gate reduction.
4 source mos transistors were reduced to 2. 1 connecting net was deleted.
2 mos transistors and 1 connecting net were deleted by split-gate reduction.