想做XILINX硬件实现自动售货机，生成比特流出错

WSND33 · 发表于 2015-8-22 13:15:52

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

您需要登录才可以下载或查看，没有账号？注册

x

如题，verilog程序写得没有问题，已做过仿真，但不知为何生成比特流总是失败，请求各位大神帮忙分析一下好嘛，万分感谢啦~（注：复位是用switch来实现）
代码如下：

module thevendor(changeten,changefive,changeone,outp,clk,sort,coin10,coin5,coin1,rst,cancel,confirm);
input clk,coin10,coin5,coin1,rst,cancel,confirm;
input [1:0] sort;
output reg [1:0] changeten;
output reg changefive;
output reg [2:0] changeone;
output reg [1:0] outp;
reg [2:0] current_state;
reg [2:0] next_state;
reg valid_juice_choice;
reg key10_current,key10_last,key5_current,key5_last,key1_current,key1_last;
reg valid_key10_input,valid_key5_input,valid_key1_input;
reg coins_full;
integer coins_sum;
reg [1:0] changeten_value;
reg changefive_value;
reg [2:0] changeone_value;
reg [1:0] outp_value;
reg input_valid;
parameter idle=3'b000;
parameter juice=3'b001;
parameter coins=3'b010;
parameter purchase=3'b011;
parameter quit=3'b100;
//选饮料
always@(posedge clk)
begin
if(sort==2'b01 | sort==2'b10 | sort==2'b11)
valid_juice_choice<=1;
else
valid_juice_choice<=0;
end
//投币
always@(posedge clk or posedge rst)
begin
if(rst)
begin
key10_current<=0;
key10_last<=0;
key5_current<=0;
key5_last<=0;
key1_current<=0;
key1_last<=0;
valid_key10_input<=1'b0;
valid_key5_input<=1'b0;
valid_key1_input<=1'b0;
end
else
begin
key10_current<=coin10;
key10_last<=key10_current;
key5_current<=coin5;
key5_last<=key5_current;
key1_current<=coin1;
key1_last<=key1_current;
if(key10_last==1'b1 && key10_current==1'b0)
valid_key10_input<=1'b1;
else if(key5_last==1'b1 && key5_current==1'b0)
valid_key5_input<=1'b1;
else if(key1_last==1'b1 && key1_current==1'b0)
valid_key1_input<=1'b1;
else begin
valid_key10_input<=1'b0;
valid_key5_input<=1'b0;
valid_key1_input<=1'b0;
end
end
end
//累加硬币
always@(posedge clk)
begin
if(!valid_juice_choice)
coins_sum<=0;
else if(input_valid)
begin
if(valid_key10_input)
coins_sum<=coins_sum+10;
else if(valid_key5_input)
coins_sum<=coins_sum+5;
else if(valid_key1_input)
coins_sum<=coins_sum+1;
else ;
end
else ;
end
//总金额够了吗
always@(posedge clk)
begin
if(sort==2'b01)
begin
if(coins_sum>=10)
begin
coins_full<=1;
input_valid<=0;
end
else
begin
coins_full<=0;
input_valid<=1;
end
end
else if(sort==2'b10)
begin
if(coins_sum>=14)
begin
coins_full<=1;
input_valid<=0;
end
else
begin
coins_full<=0;
input_valid<=1;
end
end
else if(sort==2'b11)
begin
if(coins_sum>=20)
begin
coins_full<=1;
input_valid<=0;
end
else
begin
coins_full<=0;
input_valid<=1;
end
end
else
begin
coins_full<=0;
input_valid<=1;
end
end
//出货、找零或者退款
always@(posedge clk)
begin
if(coins_full && !confirm)
begin
if(sort==2'b01)
begin
changeten_value=2'b00;
changefive_value=1'b0;
changeone_value=3'b000;
outp_value=2'b01;
end
else if(sort==2'b10)
begin
if(coins_sum==14)
begin
changeten_value=2'b00;
changefive_value=1'b0;
changeone_value=3'b000;
outp_value=2'b10;
end
else if(coins_sum==15)
begin
changeten_value=2'b00;
changefive_value=1'b0;
changeone_value=3'b001;
outp_value=2'b10;
end
else if(coins_sum==20)
begin
changeten_value=2'b00;
changefive_value=1'b1;
changeone_value=3'b001;
outp_value=2'b10;
end
else
begin
changeten_value=2'b00;
changefive_value=1'b0;
changeone_value=3'b000;
outp_value=2'b10;
end
end
else if(sort==2'b11)
begin
changeten_value=2'b00;
changefive_value=1'b0;
changeone_value=3'b000;
outp_value=2'b11;
end
else
begin
changeten_value=2'b00;
changefive_value=1'b0;
changeone_value=3'b000;
outp_value=2'b00;
end
end
else if(coins_full && cancel)
begin
if(sort==2'b01)
begin
changeten_value=2'b01;
changefive_value=1'b0;
changeone_value=3'b000;
outp_value=2'b00;
end
else if(sort==2'b10)
begin
changeten_value=2'b01;
changefive_value=1'b0;
changeone_value=3'b100;
outp_value=2'b00;
end
else if(sort==2'b11)
begin
changeten_value=2'b10;
changefive_value=1'b0;
changeone_value=3'b000;
outp_value=2'b00;
end
else
begin
changeten_value=2'b00;
changefive_value=1'b0;
changeone_value=3'b000;
outp_value=2'b00;
end
end
else
begin
changeten_value=2'b00;
changefive_value=1'b0;
changeone_value=3'b000;
outp_value=2'b00;
end
end
//状态更新逻辑
always@(posedge clk or posedge rst)
begin
if(rst)
current_state <= idle;
else
current_state <= next_state;
end
//下一状态产生逻辑
always@(confirm or cancel or current_state)
begin
case(current_state)
idle:begin
if(valid_juice_choice)
begin
if(confirm)
next_state <= juice;
else
next_state <= current_state;
end
else
next_state <= current_state;
end
juice:begin
if(coins_full)
next_state <=coins;
else
next_state <=current_state;
end
coins:begin
if(!confirm)
next_state <= purchase;
else if(cancel)
next_state <= quit;
else
next_state <= current_state;
end
purchase:begin
next_state <= current_state;
end
quit:begin
next_state <= current_state;
end
endcase
end
//输出产生逻辑
always@(current_state)
begin
case(current_state)
idle:
begin
changeten<=2'b00;
changefive<=0;
changeone<=3'b000;
outp<=2'b00;
end
juice:
begin
changeten<=2'b00;
changefive<=0;
changeone<=3'b000;
outp<=2'b00;
end
coins:
begin
changeten<=2'b00;
changefive<=0;
changeone<=3'b000;
outp<=2'b00;
end
purchase:
begin
changeten<=2'b00;
changefive<=changefive_value;
changeone<=changeone_value;
outp<=outp_value;
end
quit:
begin
changeten<=changeten_value;
changefive<=changefive_value;
changeone<=changeone_value;
outp<=2'b00;
end
endcase
end
endmodule

复制代码

错误是这样的：
ERROR:HDLCompiler:597 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 119: Module thevendor does not have a parameter named C_BASEADDR
ERROR:HDLCompiler:597 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 120: Module thevendor does not have a parameter named C_HIGHADDR
ERROR:HDLCompiler:597 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 121: Module thevendor does not have a parameter named C_SPLB_AWIDTH
ERROR:HDLCompiler:597 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 122: Module thevendor does not have a parameter named C_SPLB_DWIDTH
ERROR:HDLCompiler:597 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 123: Module thevendor does not have a parameter named C_SPLB_NUM_MASTERS
ERROR:HDLCompiler:597 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 124: Module thevendor does not have a parameter named C_SPLB_MID_WIDTH
ERROR:HDLCompiler:597 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 125: Module thevendor does not have a parameter named C_SPLB_NATIVE_DWIDTH
ERROR:HDLCompiler:597 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 126: Module thevendor does not have a parameter named C_SPLB_P2P
ERROR:HDLCompiler:597 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 127: Module thevendor does not have a parameter named C_SPLB_SUPPORT_BURSTS
ERROR:HDLCompiler:597 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 128: Module thevendor does not have a parameter named C_SPLB_SMALLEST_MASTER
ERROR:HDLCompiler:597 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 129: Module thevendor does not have a parameter named C_SPLB_CLK_PERIOD_PS
ERROR:HDLCompiler:597 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 130: Module thevendor does not have a parameter named C_INCLUDE_DPHASE_TIMER
ERROR:HDLCompiler:597 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 131: Module thevendor does not have a parameter named C_FAMILY
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 134: Cannot find port SPLB_Clk on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 135: Cannot find port SPLB_Rst on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 136: Cannot find port PLB_ABus on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 137: Cannot find port PLB_UABus on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 138: Cannot find port PLB_PAValid on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 139: Cannot find port PLB_SAValid on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 140: Cannot find port PLB_rdPrim on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 141: Cannot find port PLB_wrPrim on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 142: Cannot find port PLB_masterID on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 143: Cannot find port PLB_abort on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 144: Cannot find port PLB_busLock on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 145: Cannot find port PLB_RNW on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 146: Cannot find port PLB_BE on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 147: Cannot find port PLB_MSize on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 148: Cannot find port PLB_size on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 149: Cannot find port PLB_type on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 150: Cannot find port PLB_lockErr on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 151: Cannot find port PLB_wrDBus on this module
ERROR:HDLCompiler:267 - "E:\abcvendorthethird\hdl\system_thevendor_0_wrapper.v" Line 152: Cannot find port PLB_wrBurst on this module
ERROR:EDK:546 - Aborting XST flow execution!
ERROR:EDK:440 - platgen failed with errors!

酸牛奶加面包 · 发表于 2015-8-22 18:46:23

你的ucf呢？

ryanloi · 发表于 2015-8-22 21:20:19

怎么感觉你错误和文对不上

mballack · 发表于 2015-9-4 14:14:01

本身代码就有不规范的地方，很多else为空，组合逻辑使用<=赋值，建议还是代码风格再好好整理下吧，工具不是万能的，verilog是用来描述硬件的，不是c语言

[求助] 想做XILINX硬件实现自动售货机，生成比特流出错

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

相关帖子

站长推荐 /2