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上海展讯,内部推荐,有兴趣的同学发简历到jobhuntersh@hotmail.com.
(如果近期已经面试过的朋友,请不要重复投简历.)
以下是职位列表:
数字电路设计工程师
数字集成电路设计主管工程师
数字电路设计工程师(FPGA原型验证)
Senior SOC Integration Engineer
IC Design Manager
高级IC设计经理(CPU)
高级数字电路设计工程师(芯片bus架构设计)
高级数字电路设计工程师(DDR系统集成)
高级数字电路设计工程师(DDR IP开发)
高级数字电路设计工程师(WIFI IP开发)
以下是各个职位的具体要求:
数字电路设计工程师
工作内容/职位描述:
"1.Responsible for digital module design and chip integration.
2.Responsible for module and chip verification.
3.Also responsible for module-level lint checking, timing checking and formal verification."
任职资格:
"1.Proficiency in logic design, verification, synthesis and testing.
2.Proficiency in Verilog and its simulation environment.
3.Experience with low-power design.
4.Good knowledge of SOC design.
5.Experience in wireless communication or multimedia technologies is a plus.
6.Experience in ARM and AMBA design is a plus.
7.Experience in C_SHELL, TCL or PERL is a plus.
8.Experience in UVM, OVM or VMM is a plus.
9.Self-motivated and good team player."
数字集成电路设计主管工程师
工作内容/职位描述:
根据DE提供的RTL,release符合要求的网表文件以及相应的约束文件,并且协助PR team timing signoff.
具体工作包括 synthesis, DFT, formal check,low power check, SDC generation, STA signoff.
任职资格:
电子工程,微电子,半导体以及相关领域的本科/硕士/博士。
需要5年以上工作经验
* Proficiency in all following technology: logic synthesis ,DFT,formal check and STA
* Proficiency in related EDA tools.
* Proficiency in Verilog language.
* Experience with logic design and simulation.
* Experience with 40nm or 28nm process is a plus.
* Good knowledge of SOC design is a plus.
* Self-motivated and good team player.
数字电路设计工程师(FPGA原型验证)
工作内容/职位描述:
"FPGA-based Prototpying,
(1) Be responsible for porting SoC design into FPGA including doing partition into multiple FPGAs for large SoC design, perform FPGA implementation, i.e. RTL coding/change, simulation, synthesis, P&R.
(2) Work closely with the ASIC team & SW/HW team to support the FPGA verification for SoC design before tapeout and software development on FPGA till silicon come back.
(3) Define FPGA prototyping HW system, support the HW team on board design and bring-up of HW board.
"
任职资格:
(1) BS degree and above in EE or related majors.
(2) A minimum of 2 years industry experience in prototyping based on Xilinx or Altera device, especially Xilinx V6 & V7, Altera S4.
This means he/she has hands-on-experience in Verilog/VHDL design, simulation and FPGA implementation. Experience on doing FPGA partition for large ASIC/SoC design and achieving high frequency performance for complex and large design will be a big plus.
(3) Has strong ability of debugging and problem solving, independent work ,and self-learning.
(4) Proficiency in using lab equipments & tools, eg. Logic Analyzer, Oscilloscope.
(5) The following knowledge and skill will be plus factors.
* Experience with scripting languages like Perl, TCL C-shell.
* Familiar with SOC architecture, internal bus and the interfaces of some peripheral devices. Familiar with ARM or DSP structure.
* Knowledge of SoC design & verification methodology.
* Hardware experience, especially experience in complex HW system development based on FPGA.
* Experience with ARM-based SoC programming and debug tools.
Senior SOC Integration Engineer
工作内容/职位描述:
1. Participate in the SOC implementation, which covers from logical design, top integration to physical implementation.
2. Participate in the research of Design Methodology and tool development to improve automation and productivity.
任职资格:
1. major in CS (prefered), EE or related, Master Degree with 3 years or Bachelor with 5 years working experiences
2. good programming skill with one or more languages (e.g. tcl, perl , python, c/c++, etc) in unix/linux and a strong desire to automate flow
3. experience in ASIC design (digital design, Front-end)
4. experience in any ASIC flow and/or EDA tools (Spyglass,DesignCompiler,Primetime,ICC/Encounter etc.) is a plus
5. Be eager to learn new knowledge
6. Good communication skills and be able to work both independently and in a team
IC Design Manager
工作内容/职位描述:
能够和相关各方沟通并带领团队完成项目开发过程中和implementation相关的具体工作,包括 synthesis, DFT, formal check,low power check, SDC generation, STA signoff 。
任职资格:
"1. 电子工程,微电子,半导体以及相关领域的本科/硕士/博士。
需要8年以上工作经验,以及一年以上的管理经验
* Proficiency in all following technology: logic synthesis ,DFT,formal check and STA
* Proficiency in related EDA tools.
* Proficiency in Verilog language.
* Experience with logic design and simulation.
* Experience with 40nm or 28nm process is a plus.
* Good knowledge of SOC design is a plus.
* Self-motivated and good team player."
高级IC设计经理(CPU)
工作内容/职位描述:
1. 对芯片的设计和验证有较广泛的理解,能够其他设计团队或验证团队进行紧密合作
2. 对芯片开发的流程包括定义,设计,验证等有较好的理解
3. 能够作为一个项目经理对一个开发项目进行包括资源,交付,进度,文档等项目管理
4. 能够很好的激励团队完成富有挑战的任务
5. 能够对下属工作进行技术指导
任职资格:
1. 微电子电子或相关的电子或计算机专业硕士毕业
2. 有五年年以上IC设计或验证相关工作经验,有入式处理器设计或验证经验的优先
3. 需要有两年年管理IC设计或验证团队的管理经验,有管理嵌入式处理器设计或验证团队经验的优先
4. 需要有良好的中文和英文沟通技巧
高级数字电路设计工程师(芯片bus架构设计)
工作内容/职位描述:
"1. 芯片总线架构设计,Bus Components IP (Bridge/Matrix/monitor) 设计及功能仿真;
2. AMBA Bus 性能仿真及分析;
3.参与并指导Timing sign off和后端实现"
任职资格:
"1. 计算机、微电子等专业硕士学历;
2. 熟悉AXI/ACE等AMBA总线协议,有芯片总线架构设计经验;
3. 熟悉Qos机制,有带宽管理设计或调试经验。
4. 熟悉掌握ARM/Arteris IP者优先考虑。
高级数字电路设计工程师(DDR系统集成)
工作内容/职位描述:
"1. 负责DDR Controller/PHY 系统集成,功能仿真。
2. DDR带宽性能仿真分析;
3. DDR低功耗方案设计,DFS方案设计,仿真;
4.参与并指导Timing sign off和后端实现"
任职资格:
"1. 计算机、微电子等专业硕士学历;
2.熟悉DDR/LPDDR协议
3. 有DDR Controller/PHY开发经验;
4. 有DDR DFS开发经验,有DDR功耗和带宽性能优化经验;"
高级数字电路设计工程师(DDR IP开发)
工作内容/职位描述:
"1、研发高速高性能低功耗的LPDDR3/LPDDR4 Memory Controller & PHY。
2、协助软件开发调试DDR相关驱动,分析并定位相关问题。
3、支持芯片量产。"
任职资格:
"1、通信、微电子相关专业本科以上学历。
2、精通Verilog,熟悉ASIC流程,有四年以上芯片开发经验。
3、精通DDR相关的协议。
4、有DDR Controller、DDR PHY的实际芯片开发或验证经验。"
高级数字电路设计工程师(WIFI IP开发)
工作内容/职位描述:
"1、WiFi芯片设计,包括通信物理层、MAC层设计。
2、与系统工程师和软件工程师配合,确定软硬件分工,定义芯片结构。
3、对应系统结构和功能定义,细化后完成设计文档,并依据文档,开发RTL,实现功能。
4、对已有电路进行功能改进和功耗、面积的优化。
5、配合软件调试,支持产品量产。"
任职资格:
"1、通信、微电子相关专业本科以上学历。
2、精通Verilog,熟悉ASIC流程,有四年以上芯片开发经验。
3、熟悉802.11协议,有相关实际芯片开发经验。
4、熟悉通信原理,有TD-SCDMA、WCDMA、GSM、LTE等通信协议物理层芯片开发经验优先。" |
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