Thanks a lot.
I tried to configure the Tx_disable pin at low conditon with FPGA, but it didn't work. Today I suddenly think about that why not try to configure the Tx_diable pin at low condition with AGND net, and it finally come to a good result.
It seems that the FPGA can not configure the pin right, and it is not reasonable. Although I do not know why the FPGA control can not work, it doesn't matter.
It was your advice that as long as TXDISABLE on is LOW on both ends should have LOS low which gave me a sudden inspiration.
Thanks a lot again.