Polyphase Interpolation FIR Filter

kkk123kkk · 发表于 2007-5-11 13:08:24

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Polyphase Interpolation FIR Filter
Verilog HDL: Polyphase Interpolation FIR FilterIn a polyphase interpolation filter the output sample rate is n times the input sample rate, with n being the interpolation factor. Polyphase filters can simplify the overall design and reduce the number of computations needed. This document describes the implementation of a 16-tap low-pass finite impulse response (FIR) filter using four polyphase interpolation filter banks.
A single DSP block can implement up to four taps. By cycling the coefficients on every cycle of the 4x clock, it can implement the 16-tap FIR filter. The coefficient-loading schedule is shown in Table 1. Input samples and data are loaded in parallel and can be up to 18 bits wide.

study_enjoy · 发表于 2007-7-1 14:49:40

要有个文档就好了

yangglan · 发表于 2009-2-24 19:47:59

我也看看

aba380 · 发表于 2009-3-14 11:32:48

下来看看

lbbbb · 发表于 2009-3-30 13:56:07

看起来不错

netking · 发表于 2009-4-24 22:34:14

good post - thx..

cjchang1 · 发表于 2009-5-7 22:11:48

Thanks a lot !!!!!!!!!!!!!

manonroad · 发表于 2009-5-8 08:25:17

thanks

江南绛珠子 · 发表于 2009-5-15 20:39:49

下来看看,不过我以为是抽取的呢,下错了!

jjw3310 · 发表于 2009-5-17 19:49:19

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Polyphase Interpolation FIR Filter

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