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Polyphase Interpolation FIR Filter
Verilog HDL: Polyphase Interpolation FIR FilterIn a polyphase interpolation filter the output sample rate is n times the input sample rate, with n being the interpolation factor. Polyphase filters can simplify the overall design and reduce the number of computations needed. This document describes the implementation of a 16-tap low-pass finite impulse response (FIR) filter using four polyphase interpolation filter banks.
A single DSP block can implement up to four taps. By cycling the coefficients on every cycle of the 4x clock, it can implement the 16-tap FIR filter. The coefficient-loading schedule is shown in Table 1. Input samples and data are loaded in parallel and can be up to 18 bits wide. |
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interpolation_FIR.zip
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Verilog HDL: Polyphase Interpolation FIR Filter
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