【NVIDIA社招】上海急招芯片低功耗架构分析工程师

NVHR

【NVIDIA社招】上海急招芯片低功耗架构分析工程师

一．公司简介

        NVIDIA (英伟达™)(www.nvidia.cn)公司(纳斯达克代码：NVDA)是全球视觉计算技术的行业领袖及GPU(图形处理器)的发明者。作为高性能处理器的GPU可在工作站、个人计算机、游戏机和移动设备上生成令人叹为观止的互动图形效果。公司在全球拥有超过8000名员工，总部在加利福尼亚州圣克拉拉。

工作地址：上海研发中心【上海申江路5709号（秋月路26号）矽岸国际2号楼】

二．投递方式

简历发送至HR(Yvette SHEN)邮箱:yvettes@nvidia.com；请注明来源及申请职位

三．职位详情

Positionssummary:

1.
TegraPower Architect

o
熟悉脚本语言,有低功耗架构相关项目经验优先

2.
PowerAnalysis Engineer

o
熟悉脚本语言,有低功耗相关项目经验、ASIC前端设计经验优先

(以上岗位招多人，Junior,Senior, Staff, Specialist均在招。薪资范围：20-60W不等)

Job Description:

三．职位详情

1.Tegra Power Architect

Job Description:

Power Architect is responsible for the technical directionof Tegra (Mobile/Automotive) project from power perspective. Interacts withmultiple technologists between developers and project manages to evaluatefeasibility of requirements and determine the priorities for the development.

Responsibilities:

·
Power efficient architecture definition of SOCespecially Multi-Media modules

·
KPI use case power estimation and optimizationincluding future improvements

·
Optimize perf/Watt of present generation designsand help architect future projects

·
Guide multi-function design groups during thedesign cycle to realize the power targets

·
Design power features and work with a wide setof teams across the company

Basic Requirements:

·
Solid understanding of high-speed and low-powerdigital IPs design

·
Familiar with common SOC hardware blocks likememory controller, multi-media .etc

·
Pre-Silicon multi-media IPs design is a plus

·
Post-Silicon power/perf relative workingexperience is a plus

·
Able to coordinate low-power feature developmentcross multiple function team

2. Power Analysis Engineer

Power methodology/analysis team is responsible forresearching power expenditures and workload efficiency to identifyarchitectural, micro-architectural strategies to improve power efficiency ofthe next generation GPU and TEGRA chips.

Responsibilities:

·
Develop the power flow to automate the power expenditures measurement.

·
Evaluate new low-power technologies and improve chip power efficiency onarchitectural level.

·
Support GPU/TEGRA RTL designers using the power flow and improve theirpower efficiency on micro-arch level.

·
Understand and perform block level and chip-level power analysis.

Requirements:

·
MSEE/MSCS with experience on ASIC related areas.

·
Familiar with advanced low power techniques and high speed clockingdesired.

·
Experience in low power ASIC design/verification.

·
Programming languages: Strong Verilog (or VHDL), Strong scriptinglanguages skills, preferred Perl, TCL/python/C ++ is a plus.

·
Tool Familiarity: VCS simulation tool is must, PTPX, Synopsys DesignCompiler, Power Artist is a plus.

·
Excellent communication skills and ability to be good at teamwork.

·
Excellent English writing/speaking skills.

BestRegards,

YvetteShen

APACStaffing Team

NVIDIASHANGHAI

Building 2, No. 5709 ShenjiangRoad (No.26 Qiuyue Road)  201210.

Tel+(86 21) 61043660

yvettes@nvidia.com