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发表于 2015-6-30 17:48:30
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显示全部楼层
- module serial_check(
- clk ,
- rst_n ,
- serial_config ,
- serial_config_en,
- enable ,
- x_in ,
- z_out ,
- c_num
- );
- input clk; //clock signal
- input rst_n; //rest_signal, low active
- input[6:0] serial_config; //serial which is for compare
- input serial_config_en; //serial enable
- input enable; //enable signal, high active
- input x_in; //x input
- output z_out; //z output, high means find active serial
- output[7:0] c_num; //serial number
- wire z_out;
- reg[6:0] serial_comp;
- reg[6:0] serial_in;
- reg[7:0] c_num;
- reg[2:0] state;
- reg[2:0] nxt_state;
- parameter IDLE = 0;
- parameter CHECK = 1;
- parameter SUCCESS = 2;
- assign z_out = (nxt_state == SUCCESS);
- always@(posedge clk or negedge rst_n)
- if(!rst_n)
- serial_comp <= 0;
- else if(serial_config_en)
- serial_comp <= serial_config;
- always@(posedge clk or negedge rst_n)
- if(!rst_n)
- serial_in <= 0;
- else if(enable)
- serial_in <= (serial_in << 1) | x_in;
- always@(posedge clk or negedge rst_n)
- if(!rst_n)
- c_num <= 0;
- else if(!enable || serial_config_en)
- c_num <= 0;
- else if(state == SUCCESS)
- c_num <= c_num + 1;
-
- always@(posedge clk or negedge rst_n)
- if(!rst_n)
- state <= IDLE;
- else
- state <= nxt_state;
-
- always@(*) begin
- if(!rst_n)
- nxt_state = IDLE;
- else
- case(state)
- IDLE: if(enable)
- nxt_state = CHECK;
- else
- nxt_state = IDLE;
- CHECK:
- if(serial_in == serial_comp)
- nxt_state = SUCCESS;
- else if(enable)
- nxt_state = CHECK;
- else
- nxt_state = IDLE;
- SUCCESS:
- if(serial_in == serial_comp)
- nxt_state = SUCCESS;
- else if(enable)
- nxt_state = CHECK;
- else
- nxt_state = IDLE;
- default:
- nxt_state = IDLE;
- endcase
- end
- endmodule
复制代码
随便写了一个,不符合要求自己修改一下吧 |
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