modelsim中出现错误 Error: (vsim-3063)

鹦鹉秋

Error: (vsim-3063) H:/verilogtext/fft_ctrl/fft_top.v(65): Port 'clock' not found in the connected module (2nd connection

鹦鹉秋

** Warning: (vsim-3017) H:/verilogtext/fft_ctrl/fft_toptest.v(51): [TFMPC] - Too few port connections. Expected 12, found 10.
#         Region: /fft_toptest/m4
# ** Warning: (vsim-3722) H:/verilogtext/fft_ctrl/fft_toptest.v(51): [TFMPC] - Missing connection for port 'sink_real'.
# ** Warning: (vsim-3722) H:/verilogtext/fft_ctrl/fft_toptest.v(51): [TFMPC] - Missing connection for port 'sink_image'.
# ** Warning: (vsim-3015) H:/verilogtext/fft_ctrl/fft_top.v(38): [PCDPC] - Port size (12 or 12) does not match connection size (1) for port 'cache_ctrl_addr'. The port definition is at: H:/verilogtext/fft_ctrl/fft_ctrl.v(1).
#         Region: /fft_toptest/m4/m0
# ** Warning: (vsim-3017) H:/verilogtext/fft_ctrl/fft_top.v(56): [TFMPC] - Too few port connections. Expected 18, found 16.
#         Region: /fft_toptest/m4/m1
# ** Warning: (vsim-3015) H:/verilogtext/fft_ctrl/fft_top.v(56): [PCDPC] - Port size (18 or 18) does not match connection size (1) for port 'sink_real'. The port definition is at: H:/verilogtext/fft_ctrl/fft_bb.v(32).
#         Region: /fft_toptest/m4/m1
# ** Warning: (vsim-3015) H:/verilogtext/fft_ctrl/fft_top.v(56): [PCDPC] - Port size (18 or 18) does not match connection size (1) for port 'sink_imag'. The port definition is at: H:/verilogtext/fft_ctrl/fft_bb.v(33).
#         Region: /fft_toptest/m4/m1
# ** Warning: (vsim-3015) H:/verilogtext/fft_ctrl/fft_top.v(56): [PCDPC] - Port size (2 or 2) does not match connection size (1) for port 'source_error'. The port definition is at: H:/verilogtext/fft_ctrl/fft_bb.v(37).
#         Region: /fft_toptest/m4/m1
# ** Warning: (vsim-3015) H:/verilogtext/fft_ctrl/fft_top.v(56): [PCDPC] - Port size (6 or 6) does not match connection size (1) for port 'source_exp'. The port definition is at: H:/verilogtext/fft_ctrl/fft_bb.v(41).
#         Region: /fft_toptest/m4/m1
# ** Warning: (vsim-3015) H:/verilogtext/fft_ctrl/fft_top.v(56): [PCDPC] - Port size (18 or 18) does not match connection size (1) for port 'source_real'. The port definition is at: H:/verilogtext/fft_ctrl/fft_bb.v(42).
#         Region: /fft_toptest/m4/m1
# ** Warning: (vsim-3015) H:/verilogtext/fft_ctrl/fft_top.v(56): [PCDPC] - Port size (18 or 18) does not match connection size (1) for port 'source_imag'. The port definition is at: H:/verilogtext/fft_ctrl/fft_bb.v(43).
#         Region: /fft_toptest/m4/m1
# ** Warning: (vsim-3722) H:/verilogtext/fft_ctrl/fft_top.v(56): [TFMPC] - Missing connection for port 'inverse'.
# ** Warning: (vsim-3722) H:/verilogtext/fft_ctrl/fft_top.v(56): [TFMPC] - Missing connection for port 'sink_error'.
# ** Warning: (vsim-3017) H:/verilogtext/fft_ctrl/fft_top.v(65): [TFMPC] - Too few port connections. Expected 6, found 5.
#         Region: /fft_toptest/m4/m2
# ** Warning: (vsim-3015) H:/verilogtext/fft_ctrl/fft_top.v(65): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'address'. The port definition is at: H:/verilogtext/fft_ctrl/srams_bb.v(35).
#         Region: /fft_toptest/m4/m2
# ** Error: (vsim-3063) H:/verilogtext/fft_ctrl/fft_top.v(65): Port 'clock' not found in the connected module (2nd connection).
#         Region: /fft_toptest/m4/m2
# ** Warning: (vsim-3015) H:/verilogtext/fft_ctrl/fft_top.v(65): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'data'. The port definition is at: H:/verilogtext/fft_ctrl/srams_bb.v(36).
#         Region: /fft_toptest/m4/m2
# ** Warning: (vsim-3015) H:/verilogtext/fft_ctrl/fft_top.v(65): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'q'. The port definition is at: H:/verilogtext/fft_ctrl/srams_bb.v(40).
#         Region: /fft_toptest/m4/m2
# ** Warning: (vsim-3722) H:/verilogtext/fft_ctrl/fft_top.v(65): [TFMPC] - Missing connection for port 'inclock'.
# ** Warning: (vsim-3722) H:/verilogtext/fft_ctrl/fft_top.v(65): [TFMPC] - Missing connection for port 'outclock'.
# ** Warning: (vsim-3015) H:/verilogtext/fft_ctrl/fft_top.v(74): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'address'. The port definition is at: H:/verilogtext/fft_ctrl/sram_bb.v(35).
#         Region: /fft_toptest/m4/m3
# ** Warning: (vsim-3015) H:/verilogtext/fft_ctrl/fft_top.v(74): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'data'. The port definition is at: H:/verilogtext/fft_ctrl/sram_bb.v(37).
#         Region: /fft_toptest/m4/m3
# ** Warning: (vsim-3015) H:/verilogtext/fft_ctrl/fft_top.v(74): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'q'. The port definition is at: H:/verilogtext/fft_ctrl/sram_bb.v(39).
#         Region: /fft_toptest/m4/m3

fpgaqin

testbench例化，里面少了   .clock  (clock),

鹦鹉秋

回复 3# fpgaqin
谢谢啊