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[招聘] 厦门asic岗位招聘

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发表于 2015-6-5 20:55:05 | 显示全部楼层 |阅读模式

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厦门asic岗位招聘。应届和社招均欢迎,本科硕士均欢迎。
做手机芯片的,国内没几家,一搜就知道名字了。
简历请发邮箱 shuli198349@163.com

//////////////////////////////////////////////////////////////////////////////////////////////////////////
1:SOC/IP 数字电路设计工程师-厦门工作内容/职位描述:

1. Responsible for IPs design/verification and SOC/SUBSYS design/integration/verifications.
2. Responsible for IPs/SOC design FPGA emulation/verification.
3. Responsible for chip verification and performance analysis and correlation.
4. Responsible for ASIC mass production.
任职资格:

1. 2+ years working experience. Proficiency in logic design, verification, synthesis, and testing.
2. Proficiency in Verilog design, simulation, and debugging.
3. Good with low power design methodologies.
4. Good with SOC design knowledge.
5. Good with wireless communication, multimedia, ISP, 2D/3D graphic, etc. knowledge.
6. Good with ARM CPUs and relative AMBA bus design experiences.
7. Good with C-Shell, TCL or Perl experiences.
8. Good with UVM, OVM or VMM experiences.
9. Self-motivated and good team work.

//////////////////////////////////////////////////////////////////////////////////////////////////////////
2:SOC 整合流程设计工程师-厦门工作内容/职位描述:

1. Responsible for SOC frontend flow development : synthesis, low power, DFT/BIST, floorplan/CTS, STA/sign-off, SI/PI analysis, etc.
2. Responsible for SOC mass production CP/FT/MT issues clarifying/solving.
3. Responsible for chip performance characterization and bench correlation.
4. Responsible for test cost reduction and quality improvement.
5. Responsible for advanced sub-micron technology frontend flow development.
任职资格:

1. 2+ years working experience, proficiency in logic and digital circuit design
2. Good with nLint, synthesis, LEC, STA, CTS, DFT/BIST, low power design, etc. experiences.
3. Familiar with UNIX/LINUX, TCL, Perl, C-Shell, etc.
4. Self-motivated and good team work.


//////////////////////////////////////////////////////////////////////////////////////////////////////////
3:SOC设计验证&效能分析工程师工作内容/职位描述:

1. Responsible for IPs/SOC design verification/regression through efficient methodologies.
2. Responsible for SOC system performance evaluation (ESL).
3. Responsible for SOC hardware/software co-emulation, analysis, and verification.
任职资格:

1. 2+ years working experience, proficiency in logic design
2. Good with ARM/microprocessor/computer archiecture knowledge.
3. Preferably mathematical/statistical analysis background.
4. Good with UNIX/C/C++, TCL, Makefile, Perl or Python.
5. Good with UVM, OVM or VMM experiences.
6. Good with Assertion-based verification/SVA.
7. Self-motivated and good team work.
发表于 2015-6-7 15:54:24 | 显示全部楼层
顶LZ!!!!!
发表于 2015-6-7 22:52:06 | 显示全部楼层
赞一个
发表于 2015-6-8 10:19:05 | 显示全部楼层
不错的啊
 楼主| 发表于 2015-6-8 23:09:29 | 显示全部楼层
莫沉了,顶起来~~~
长期有效啊~~~~
 楼主| 发表于 2015-6-10 09:25:49 | 显示全部楼层
各位不好意思,前面手机邮箱出问题了,没有看到邮件。
简历已收到的我都回复了,合适的我会尽快电话联系,谢谢。
 楼主| 发表于 2015-6-10 09:28:23 | 显示全部楼层
不好意思,前面手机邮箱出问题了,没有看到邮件。
简历已收到的我都回复了,如果合适我会尽快电话联系,谢谢。
 楼主| 发表于 2015-6-16 10:11:48 | 显示全部楼层
继续,一直有效。
发表于 2015-6-16 10:34:50 | 显示全部楼层
请问昨天贵公司给我打电话,但是我的简历是以前的,有些情况在电话里面忘说了,该怎么更新简历呢?
发表于 2015-6-16 10:34:57 | 显示全部楼层

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本帖最后由 chen1q 于 2015-6-16 10:37 编辑

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