为什么使用VerilogA混合仿真时，一瞬间就仿真完了

pigintree

fs=1M，开关，运放和一部分数字模块都是veriloga模型。仿真时间设为900uS时很正常，仿真时间设为1mS以上时就瞬间仿完了，但输出波形是乱的，是怎么回事啊？？哪位遇到过吗也说仿真成功了，没报什么错误


Number of accepted tran steps = 54.
Initial condition solution time = 20 ms.
Intrinsic tran analysis time = 110 ms.
Total time required for tran analysis `tran' was 140 ms.


finalTimeOP: writing operating point information to rawfile.
modelParameter: writing model parameter values to rawfile.
element: writing instance parameter values to rawfile.
outputParameter: writing output parameter values to rawfile.
designParamVals: writing netlist parameters to rawfile.