在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 2363|回复: 0

[招聘] MPS芯源系统成都招聘-电子类硕士毕业生

[复制链接]
发表于 2015-5-15 16:05:32 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
MPS芯源系统 www.monolithicpower.com
联系方式:杰思猎头jessie 0755-86609589  jessiepu@jshrconsult.com  qq:1578300951 微信:15818618377

Position: Digital Application Engineer电子类硕士应届毕业生/本科5年以上数字逻辑电路设计工作经验
Subordinates: 0
Location: Chengdu
Summary:
This position is set to support MPS new product application qualification, provide technical support for customer and take care of product related technical document.
RESPONSIBILITIES:
1 Define MPS's future digital power IC;
2 The primary responsibility is designing, developing, troubleshooting and debugging programs on FPGA platforms;
3 Perform functional verification of designs on block and chip level.
4 Design and debug the analog circuit to implement the new function defined.
5 The responsibilities include the development of new features and products, and support the designer to implement the new products.
REQUIREMENTS:
1 MSEE or equivalent;
2 Good at the DSP or MCU processor, familiar with FPGA will be better;
3 Capable of digital and analog circuit design, familiar with the operation of ADC and DAC;
4 Excellent communication, writing and presentation skills;
5 Fluent communication skills in English;
6 Experience in a power industry or power management IC company will be better

Position: Yield Enhancement Engineer电子类硕士/本科应届毕业生
Subordinates: 0
Location: Chengdu
Summary:
This position is set for yield enhancement engineer to support released products shipment, daily on hold lot disposition, fab transfer qualification, mask change qualification, bump house transfer qualification, yield improvement and product quality improvement.
RESPONSIBILITIES:
(1) Dispose the on hold lots daily;
(2) Low yield product analysis, yield enhancement.
(3) Circuit/Mask change qualification and release.
(4) Process modification qualification.
(5) Responsible for process transfer from Fab A to Fab B.
(6) Responsible for products cost reduction related work
(7) Customer support
REQUIREMENTS:
1) Bachelor and Master, major is semiconductor related.
2) Has a good knowledge of analog circuitry, device physics and process.
3) Has good English communication skills in both speaking and writing.

Position: Test Engineer电子类硕士应届毕业生/本科5年以上工作经验
Subordinates: 0
Location: Chengdu
Summary:
Develop test solutions for new defined products, including Test Plan, Test hardware and test program. This test solution is subject to release to testfloor for mass production.
RESPONSIBILITIES:
1. Develop test plans for new defined products (relatively easier products) along with Design Engineers and Product Engineers;
2. With the help of TE Supervisors, design test hardware and software for new defined products based on our existing test platform: ASL-1000 and ETS-88;
3. Collect data during new product development and feedback to other R&D groups under the supervising of TE Supervisors;
4. Qualify the test hardware and program to release to production;
5. Sustain test hardware and program during production to solve any test related issues.
6. Perform other tasks assigned by superior.
REQUIREMENTS:
1. Master degree in Electrical Engineering or equivalent
2. Knowledge of Analog circuit analysis;
3. C/C++ language coding;
4. Good at English writing and reading;
5. Basic knowledge of Office software.
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

小黑屋| 手机版| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-11-5 14:45 , Processed in 0.020491 second(s), 8 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表