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不知道什么原因，各位大神看看这是测试代码
`timescale 1 ps/ 1 ps
`include "led.v"
`include "left.v"
`include "right.v"
`include "divid.v"
module led_vlg_tst();
reg brake_in;
reg clk;
reg lt;
reg rst;
reg rt;
// wires
wire [5:3] led1;
wire [2:0] led2;
led u1(
.brake_in(brake_in),
.clk(clk),
.led1(led1),
.led2(led2),
.lt(lt),
.rst(rst),
.rt(rt)
);
parameter DELY=50;
always #(DELY) clk=~clk;
initial begin
rst=0;clk=0;lt=0;rt=0;brake_in=0;
#DELY
rst=0;lt=1;rt=0;brake_in=0;
#DELY
rst=1;lt=1;rt=0;brake_in=0;
#DELY rst=1;lt=0;rt=1;brake_in=0;
#DELY rst=1;lt=0;rt=0;brake_in=1;
#DELY
rst=1;lt=1;rt=0;brake_in=1;
#DELY
rst=1;lt=0;rt=1;brake_in=1;
end
initial $monitor($time,,,"rst=%b rt=%b lt=%b brake_in=%b led1=%d led2=%d",rst,rt,lt,brake_in,led1,led2);
endmodule
这是顶层代码
module led(
rst,
clk,
brake_in,
lt,
rt,
led1,
led2
);
input wire
rst;
input wire
clk;
input wire
brake_in;
input wire
lt;
input wire
rt;
output wire
[5:3] led1;
output wire
[2:0] led2;
wire
SYNTHESIZED_WIRE_2;
right
b2v_inst(
.rt(rt),
.clk(SYNTHESIZED_WIRE_2),
.brake_in(brake_in),
.rst(rst),
.led1(led1));
defparam
b2v_inst.s0 = 3'b000;
defparam
b2v_inst.s1 = 3'b001;
defparam
b2v_inst.s2 = 3'b010;
defparam
b2v_inst.s3 = 3'b100;
defparam
b2v_inst.s4 = 3'b111;
left
b2v_inst1(
.lt(lt),
.clk(SYNTHESIZED_WIRE_2),
.brake_in(brake_in),
.rst(rst),
.led2(led2));
defparam
b2v_inst1.s0 = 3'b000;
defparam
b2v_inst1.s1 = 3'b001;
defparam
b2v_inst1.s2 = 3'b010;
defparam
b2v_inst1.s3 = 3'b100;
defparam
b2v_inst1.s4 = 3'b111;
divd
b2v_inst2(
.reset(rst),
.clkin(clk),
.clkout(SYNTHESIZED_WIRE_2));
endmodule
下面是各模块代码
左模块
module left(lt,clk,led2,brake_in,rst);
input clk,lt,brake_in,rst;
output led2;
reg[2:0] led2;
reg[2:0] state,next_state;
parameter s0=3'b000;
parameter s1=3'b001;
parameter s2=3'b010;
parameter s3=3'b100;
parameter s4=3'b111;
always@(posedge clk or negedge rst )//异æ-￥清零
begin
if(!rst) state<=s0;//低ç”μå13清零（rst高ç”μå13有效）
else
if(!(lt||brake_in)) state<=s0;
else
state<=next_state;
end
always@(state or brake_in)
begin
case(state)
s0:begin if(brake_in) next_state<=s4;
else next_state<=s1;end
s1:begin if(brake_in) next_state<=s4;
else next_state<=s2;end
s2:begin if(brake_in) next_state<=s4;
else next_state<=s3;end
s3:begin if(brake_in) next_state<=s4;
else next_state<=s1;end
s4:begin if(brake_in) next_state<=s0;
else next_state<=s1;end
endcase
led2<=state;
end
endmodule
右模块
module right(rt,clk,led1,brake_in,rst);
input clk,rt,brake_in,rst;
output led1;
reg[2:0] led1;
reg[2:0] state,next_state;
parameter s0=3'b000;
parameter s1=3'b001;
parameter s2=3'b010;
parameter s3=3'b100;
parameter s4=3'b111;
always@(posedge clk or negedge rst )//异æ-￥清零
begin
if(!rst) state<=s0;//低ç”μå13清零（rst高ç”μå13有效）
else
if(!(rt||brake_in)) state<=s0;
else
state<=next_state;
end
always@(state or brake_in)
begin
case(state)
s0:begin if(brake_in) next_state<=s4;
else next_state<=s1;end
s1:begin if(brake_in) next_state<=s4;
else next_state<=s2;end
s2:begin if(brake_in) next_state<=s4;
else next_state<=s3;end
s3:begin if(brake_in) next_state<=s4;
else next_state<=s1;end
s4:begin if(brake_in) next_state<=s0;
else next_state<=s1;end
endcase
led1<=state;
end
endmodule
分频
module divd(reset,clkin,clkout);
input reset,clkin;
output clkout;
reg clkout;
reg [23:0] cnt;
always @ (negedge reset or posedge clkin)
if(reset==1'b0)
begin
cnt=0;
clkout=0;
end
else
begin
cnt=cnt+1'b1;
if(cnt>=5000000)
begin
cnt=0;
clkout=~clkout;
end
end
endmodule
弄了半天，找不到问题，各位大神帮帮忙 |
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2015-5-3 17:55:37
