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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SPI3578 IS
GENERIC(
N_WAITCLK : INTEGER := 10;
N_DELAYCLK : INTEGER := 4
);
PORT(
ICLK
: IN STD_LOGIC;
IRESET
: IN STD_LOGIC;
IEN : IN STD_LOGIC;
SPICLK
: OUT STD_LOGIC;
SDO
: IN STD_LOGIC;
SDI
: OUT STD_LOGIC;
CS
: OUT STD_LOGIC;
DATAIN
: IN
STD_LOGIC_VECTOR(15 DOWNTO 0);
DATAOUT : OUT
STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE BEHAVIOR OF SPI3578 IS
TYPE SPI_STATE IS (S0_IDLE,S1_REP,S2_PLACE,S3_RECIVE,S4_DELAY);
SIGNAL CURRENT_STATE,NEXT_STATE : SPI_STATE;
SIGNAL CNT ,NDLAY : INTEGER RANGE 0 TO 127;
SIGNAL BITL
:INTEGER RANGE 0 TO 15;
SIGNAL SCLK
: STD_LOGIC := '0';
SIGNAL TX_DATA
: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL RX_DATA
: STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
STATE_RENEW
 ROCESS(ICLK,IRESET)
BEGIN
IF RISING_EDGE(ICLK)
THEN
IF (IRESET ='0')
THEN
CURRENT_STATE
<= S0_IDLE;
SPICLK
<= '0';
CS
<= '1';
ELSE
CURRENT_STATE
<= NEXT_STATE;
END IF;
END IF;
END PROCESS;
STATE_CREATROCESS(CURRENT_STATE,IEN,ICLK)
BEGIN
CASE (CURRENT_STATE) IS
WHEN S0_IDLE
=>
IF IEN = '1' THEN
NEXT_STATE <= S0_IDLE;
CNT <= 0;
CS <= '1';
ELSE
NEXT_STATE
<= S1_REP;
END IF;
WHEN S1_REP
=>
IF CNT <= N_WAITCLK THEN
CNT <= CNT + 1;
NEXT_STATE <= S1_REP;
ELSE
NEXT_STATE <= S2_PLACE;
BITL <= 0;
END IF;
WHEN S2_PLACE
=>
SDI <= TX_DATA(15-BITL);
SCLK <= NOT SCLK;
SPICLK
<=
SCLK;
NEXT_STATE <= S3_RECIVE;
WHEN S3_RECIVE
=>
TX_DATA(15-BITL)<= SDO;
SCLK <= NOT SCLK;
SPICLK
<=
SCLK;
IF BITL
<= 14
THEN
BITL
<= BITL + 1;
NEXT_STATE <= S2_PLACE;
ELSE
NEXT_STATE <= S4_DELAY;
END IF;
WHEN S4_DELAY
=>
IF NDLAY <= N_DELAYCLK THEN
NEXT_STATE <=S4_DELAY;
NDLAY
<=
NDLAY +1;
ELSE
NEXT_STATE <= S0_IDLE;
END IF;
WHEN OTHERS
=> NULL;
END CASE;
END PROCESS;
--SPICLK
<=
SCLK;
END BEHAVIOR ; |
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发表于 2015-4-17 22:22:12
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