并行总线 FPGA读取数据出现问题

sundonga · 发表于 2015-4-1 23:12:10

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本帖最后由 sundonga 于 2015-4-1 23:15 编辑

大家好，我写了一段程序来与PCI9052接口，由PCI9052来读写FPGA几个寄存器的数据。下图是逻辑分析仪得到的时序图，本来应该读到的是0x34，就是逻辑分析仪图里红色方框里的TED7~TED0的值，可不知道为什么实际会读成0xb5，程序是状态机写的，附在后面，大家帮忙看看这是怎么回事？谢过！

------------------------------------------
process(CLK)
begin
if(CLK='1' and CLK'event) then
if RSTn='0' then
CURRENT_STATE <= IDLE_STATE;
TED(15 downto 0)<=(others => 'Z');
TLRDYn <= '1';
led_out <= X"00";
else
case CURRENT_STATE is
when IDLE_STATE =>
TLRDYn <= '1';
TED(15 DOWNTO 0) <= (others => 'Z');
if ((not TADSn) and TLWorRn and (not TCS1n))= '1' then
CURRENT_STATE <= WR_START_STATE;
elsif ((not TADSn) and (not TLWorRn) and (not TCS1n))= '1' then
CURRENT_STATE <= RD_START_STATE;
else
CURRENT_STATE <= IDLE_STATE;
end if;
when WR_START_STATE =>
--led_out <= X"FF";
if TWRn = '0' then
CURRENT_STATE <= WR_WAIT_STATE;
else
CURRENT_STATE <= WR_START_STATE;
end if;
when WR_WAIT_STATE =>
--led_out <= X"AA";
CURRENT_STATE <= WR_ACCEPT_STATE;
when WR_ACCEPT_STATE =>
IF(TBE1n = '0') THEN
CASE TEA IS
WHEN ADR_tempd => tempd(15 DOWNTO 0) <= TED(15 DOWNTO 0);
led_out <= X"FF";
WHEN ADR_tempe => tempe(15 DOWNTO 0) <= TED(15 DOWNTO 0);
WHEN ADR_tempf => tempf(15 DOWNTO 0) <= TED(15 DOWNTO 0);
WHEN ADR_tempg => tempg(15 DOWNTO 0) <= TED(15 DOWNTO 0);
WHEN ADR_temph => temph(15 DOWNTO 0) <= TED(15 DOWNTO 0);
WHEN ADR_tempi => tempi(15 DOWNTO 0) <= TED(15 DOWNTO 0);
WHEN OTHERS => NULL;
END CASE;
END IF;
IF(TBE1n = '1') THEN
CASE TEA IS
WHEN ADR_tempd => tempd(31 DOWNTO 16) <= TED(15 DOWNTO 0);
WHEN ADR_tempe => tempe(31 DOWNTO 16) <= TED(15 DOWNTO 0);
WHEN ADR_tempf => tempf(31 DOWNTO 16) <= TED(15 DOWNTO 0);
WHEN ADR_tempg => tempg(31 DOWNTO 16) <= TED(15 DOWNTO 0);
WHEN ADR_temph => temph(31 DOWNTO 16) <= TED(15 DOWNTO 0);
WHEN ADR_tempi => tempi(31 DOWNTO 16) <= TED(15 DOWNTO 0);
WHEN OTHERS => NULL;
END CASE;
END IF;
--led_out <= X"33";
CURRENT_STATE <= WR_READY_STATE;
when WR_READY_STATE =>
--led_out <= X"AF";
CURRENT_STATE <= IDLE_STATE;
TLRDYn <= '0';
when WR_END_STATE =>
CURRENT_STATE <= IDLE_STATE;
TLRDYn <= '1';
------------------------RD-------------------------------------------------------
when RD_START_STATE =>
if TRDn = '0' then
CURRENT_STATE <= RD_WAIT_STATE;
else
CURRENT_STATE <= RD_START_STATE;
end if;
when RD_WAIT_STATE =>
CURRENT_STATE <= WR_ACCEPT_STATE;
when RD_ACCEPT_STATE =>
IF(TBE1n = '0') THEN
CASE TEA IS
WHEN ADR_tempd => TED(15 downto 0) <=tempd(15 DOWNTO 0);
WHEN ADR_tempe => TED(15 DOWNTO 0) <=tempe(15 DOWNTO 0);
--led_out <= X"EE";
WHEN ADR_tempf => TED(15 DOWNTO 0) <=tempf(15 DOWNTO 0);
WHEN ADR_tempg => TED(15 DOWNTO 0) <=tempg(15 DOWNTO 0);
WHEN ADR_temph => TED(15 DOWNTO 0) <=temph(15 DOWNTO 0);
WHEN ADR_tempi => TED(15 DOWNTO 0) <=tempi(15 DOWNTO 0);
WHEN OTHERS => TED(15 downto 0)<= X"FFFF";--(others => 'Z');
END CASE;
END IF;
IF(TBE1n = '1') THEN
CASE TEA IS
WHEN ADR_tempd => TED(15 DOWNTO 0) <=tempd(31 DOWNTO 16);
--led_out <= X"DD";
WHEN ADR_tempe => TED(15 DOWNTO 0) <=tempe(31 DOWNTO 16);
--led_out <= X"EE";
WHEN ADR_tempf => TED(15 DOWNTO 0) <=tempf(31 DOWNTO 16);
WHEN ADR_tempg => TED(15 DOWNTO 0) <=tempg(31 DOWNTO 16);
WHEN ADR_temph => TED(15 DOWNTO 0) <=temph(31 DOWNTO 16);
WHEN ADR_tempi => TED(15 DOWNTO 0) <=tempi(31 DOWNTO 16);
WHEN OTHERS => TED(15 downto 0)<= X"FFFF";--(others => 'Z');
--led_out <= X"FF";
END CASE;
END IF;
CURRENT_STATE <= RD_WAIT2_STATE;
when RD_WAIT2_STATE => --多一个等待周期，让数据稳定之后再发READY
CURRENT_STATE <= RD_READY_STATE;
when RD_READY_STATE =>
CURRENT_STATE <= IDLE_STATE;
TLRDYn <= '0';
when RD_END_STATE =>
CURRENT_STATE <= IDLE_STATE;
TLRDYn <= '1';
when others => CURRENT_STATE <= IDLE_STATE;
end case;
end if;
end if;
end process;

复制代码

董小三 · 发表于 2015-4-2 07:37:14

逻辑分析仪抓到的数据是对的，看是不是软件的问题

sundonga · 发表于 2015-4-2 10:24:53

回复 2# 董小三

你说上位机的软件，应该没问题，因为是测试用的只有读和写这个寄存器，没有别的功能。而且板子上恰好有几个LED灯，我用LED显示了一下那个寄存器的值，确实是错了。不知道什么会导致读回来错误的值。

sundonga · 发表于 2015-4-2 20:11:08

谢谢各位，原因找到了，是状态机跳错了状态。

[求助] 并行总线 FPGA读取数据出现问题

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