【AMD热招】上海MTS ASIC Design Verification engineer (NBIO)

RecruiterAMD

AMD上海研发中心热招 MTS asic Design Verification engineer (NBIO)，请感兴趣的把简历发送至
nina.zhang@amd.com; 并注明“所应聘职位_姓名_学历_工作年限”，谢谢。

JobResponsibilities:

AMD NBIO (North Bridge IO) team delivers industry leading high performanceinterconnects IP for all AMD products including dGPU, APU, Server and Gameconsoles. You'll be working with the global team on NBIO subsystem levelverification, and provide deployment support to various global SOC teams

Responsibility:
* Work with architecture/IP designers to get a full deep insight on the designunder test
* Subsystem level test plan development and SOC test plan consultant

* Subsystem level test bench setup/maintain, methodology deployment,verification component create/maintain
* Test case create/triage to ensure complete coverage
* Deploy NBIO or provide technical consult support to SOC teams

Job Requirements:
Education& Qualifications:

1. Candidate is preferred to be MSEE with minimum of 5 years, or BSEE withminimum of 7-year experience in digital ASIC/SOC design verification.

Experience:

1. Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC (Strongknowledge of SoC integration technique and methodology )or Processor (cpu orGPU) or Industry bus standard (PCI-e, HT, USB, DDR, DisplayPort) ormultimedia/video is preferred.
2. Good knowledge of Systemverilog and OVM is a plus.
3. Good knowledge of Verilog/C/C++/System C/SystemVerilog.
4. Verification insights into random techniques.
5. Verification of large scale ASICs.
6. Strong knowledge of low-power design technique and implementation flow

7. Verification of Virtualization Components is an asset.
8. Strong C and C++ software development and scripting languages (Perl, CShell, Makefile, …) experience.
9. Solid background with hardware verification methodologies such ascoverage-based verification methodology with the use of hardware assertions(PSL or SVA).
10. Familiar with ASIC EDA tools, i.e. DCT, Primetime, Formality, Z-in…
11. Proficient in STA and multiple clocking design
12. Strong cooperation skill with global team
13. Strong cooperation skill with global team
14. Good at English for communication in talking/writing/reading
15. Experience of team lead is plus
16. Experience of tape-out using 40nm or advanced technology is plus
17. Technical publication/paper, i.e. SNUG is plus
18. Strong self-motivation
19. Be open, passion and capability to work under high pressure