Cadence SH 招聘高级数字后端产品测试工程师

kengteng

Cadence SH 招聘高级数字后端产品测试工程师       
Job location: Shanghai

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If you have interest, PLS send your update CV to zhangyl@cadence.com

1.   Lead/Senior Product Validation Engineer (Lower Power and Static Timing Analysis)   
欢迎有工作经验人士和应届博士、硕士生投递
Position Description:
1. Identify Low Power solution and timing sign-off challenges in complex SOC designs and advanced process nodes
2. Proactively provide Low Power & STA development suggestions to R&D.
3. Build up Lower Power & STA expertise and deliver support to field team and customers whenever needed.
4. Required to acquire expertise and ownership over existing product components as well as develop brand new product features.
5. Project leader on important Low Power or STA features.
  
Position Requirements:
1. Bachelor with 5 years related experience or Master with 2 years related experience in design house, FAB or EDA Company.
2. Rich experience in IC design flow (front-end or back-end).
3. Experience in Low Power flow (CPF or IEEE1801), knowledge in timing closure is a strong plus.
4. Good Unix System knowledge and script skill of TCL/TK/CSH/PERL.
5. Excellent capability of self-learning, problem solving skills;
6. Be proactive and self-motivated;
7. Strong leadership;
8. Good written English and oral English is a strong plus

2. Senior Product Validation Engineer (for GPS)
Position Description:
This engineer will work in Encounter GPS (Global Physical Synthesis) product validation team. The responsibilities include:
a) Assist in Cadence EDI development and validation
b) Validate and maintain comprehensive GPS unit and flow test cases for Encounter Digital Implementation System.
c) Develop test suites of the new features of EDI GPS function
  
Position Requirements:
a)MS of EE/CS
b)Digital IC design knowledge is necessary, statistic timing analysis knowledge is a strong plus
c)Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.
d)Good communication in English and Chinese, good confidence and self-motivation.