Cadence SH 招聘高级数字后端产品测试工程师

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Cadence SH 招聘高级数字后端产品测试工程师

Joblocation: Shanghai

更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘

If you haveinterest, PLS send your update CV to zhangyl@cadence.com

1.   Lead/Senior Product Validation Engineer(Lower Power and Static Timing Analysis)   

欢迎有工作经验人士和应届博士、硕士生投递

PositionDescription:

1. Identify Low Powersolution and timing sign-off challenges in complex SOC designs and advancedprocess nodes

2. Proactively provide LowPower & STA development suggestions to R&D.

3. Build up Lower Power& STA expertise and deliver support to field team and customers wheneverneeded.

4. Required to acquireexpertise and ownership over existing product components as well as developbrand new product features.

5. Project leader onimportant Low Power or STA features.

  

PositionRequirements:

1. Bachelor with 5 yearsrelated experience or Master with 2 years related experience in design house,FAB or EDA Company.

2. Rich experience in ICdesign flow (front-end or back-end).

3. Experience in Low Powerflow (CPF or IEEE1801), knowledge in timing closure is a strong plus.

4. Good Unix Systemknowledge and script skill of TCL/TK/CSH/PERL.

5. Excellent capability ofself-learning, problem solving skills;

6. Be proactive andself-motivated;

7. Strong leadership;

8. Good written English andoral English is a strong plus

2. Senior ProductValidation Engineer (for GPS)

PositionDescription:

This engineer will work in Encounter GPS (Global PhysicalSynthesis) product validation team. The responsibilities include:

a) Assistin Cadence EDI development and validation

b) Validateand maintain comprehensive GPS unit and flow test cases for Encounter Digital ImplementationSystem.

c) Develop testsuites of the new features of EDI GPS function

  

Position Requirements:

a)MS ofEE/CS

b)DigitalIC design knowledge is necessary, statistic timing analysis knowledge is astrong plus

c)UnixSystem knowledge, vi/TCL/TK/CSH/Perl will be plus.

d)Goodcommunication in English and Chinese, good confidence and self-motivation.