诚招Staff Verification Engineer,地点：上海。

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某公司诚招Staff Verification Engineer,地点：上海。如有兴趣，欢迎添加微信：taiyanqian或QQ：970890075了解详细的信息

Qualifications
-MS in EE/CS/ME.
-Minimum of five  years experience.
-Additional qualifications include: Good IC verification skills and basicknowledge of logic and circuit design, good communication and problem solvingskills.
-Candidate should be familiar with as System Verilog, VMM/OVM/UVM verificationmethdology.

-Candidateshould be familiar with industry standard ASIC design and verification toolsand flow.

-Goodknowledge DDR protocol and computer system achitecture would be an addedadvantage.

-Goodknowledge of Perl and shell programming would be an added advantage.

Responsibilities:
-Understanding the expected functionality of designs.
-Developing testing and regression plans.
-Designing and developing verification environment.
-Running RTL and gate-level simulations/regression.
-Code/functional coverage development, analysis and closure.

Requirements:
Experience & Skill: 5 Years
-Design verification experience (test plan, test bench, assertions, debuggingdesigns, code coverage etc.).
-Knowledge in ASIC/FPGA design process and verification tools.
-Familiar with design and verification languages (Verilog, System Verilog, SVAetc.).
- Scripting and automation skills (tcl, perl, makefile etc) a plus.
-Familiar with C/C++.
-Knowledge of DDR protocol a plus.
-Independent and self-managing.

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