Cadence SH 招聘Lead Application Engineer

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Cadence SH 招聘Lead Application EngineerIf you have interest, please send your update CV to zhangyl@cadence.com
Position Description:1)The candidates should be senior in a way that they are not only technicalexcellent but also mature & able to talk to customers, advise customers aswell as other, following team members. This engineer should have excellentdesign experiences in the digital implementation domain including Floorplan,P&R, STA, Physical verification, DFM.2)The engineer must have a solid background in circuits, electronics &physics & should be very willing to learn new stuff.3)Key Accountabilities: Ability to handle large sized design implementation tasks& architectural tasks alone. Ability to assess Customer's Designenvironment, to understand his application needs & to build new Designenvironment based on specifications & available Cadence tool technology.4)Ability to acquire a basic understanding of the (services) business environmentof Cadence. Feeling responsible for technical delivery as well as businessdevelopment & opportunity creation.5)Behavioral competencies: Teamwork; Customer focus; Accountability;Communication; Leadership; Proactive; PositionRequirements:         Essential Qualifications:1) MS degreewith 5+/7+ years of applicable experiencein electrical engineering, microelectronics.2)Essential that the individual demonstrates strong communication, verbal andwritten, and reporting skills.3)Good verbal and written communication skill in English is needed. DesirableQualifications:1)Will have demonstrated hands-on experience and expertise with Cadence logicaland physical design tools ( SoC Encounter, Conformal, QRC, Vstorm, ETS, PVS) orequivalent tools, flows and methodologies required to execute a physical designproject.2)Will have demonstrated successful completion of chip tapeout  (40nm/andbelow tapeout and/or hierarchical implementation experience are a real plus) asan individual contributor3) Is able to work on-site atcustomer premises, travel up to 30%, and put in long hours when required tomeet customer deadline.4)Experience in sign-off tools for STA, IR drop, power analysis, SI analysis is aplus5) ARM core implementationexperience is definitively a plus.