数字VLSI芯片设计——使用Cadence和Synopsys_CAD工具(英文版)

jellyld · 发表于 2015-1-4 20:54:00

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

您需要登录才可以下载或查看，没有账号？注册

x

如题，非常好的VLSI教程，各章节为独立彩色pdf文件，目录如下
Crafting a Chip
A Practical Guide to the UofU VLSI CAD Flow Erik BrunvandSchool of Computing University of Utah
August 24, 2006
Draft August 24, 2006 2
Contents
1 Introduction 9
1.1 Cad Tool Flows . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Cadence ICFB 15
2.1 Cadence Design Framework . . . . . . . . . . . . . . . . . 15
2.2 Starting Cadence . . . . . . . . . . . . . . . . . . . . . . . 17
3 Composer Schematic Capture 23
3.1 Starting Cadence and Making a new Working Library . . . . 24
3.2 Creating a New Cell . . . . . . . . . . . . . . . . . . . . . . 25
3.3 Schematics that use Transistors . . . . . . . . . . . . . . . . 35
3.4 Printing Schematics . . . . . . . . . . . . . . . . . . . . . . 38
3.4.1 Modifying Postscript Plot Files . . . . . . . . . . . 42
3.5 Variable, Pin, and Cell Naming Restrictions . . . . . . . . . 43
4 Verilog Simulation 45
4.1 Verilog Simulation of Composer Schematics . . . . . . . . . 48
4.1.1 Verilog-XL: Simulating a Schematic . . . . . . . . 49
4.1.2 NC Verilog: Simulating a Schematic . . . . . . . . 67
4.2 Behavioral Verilog Code in Composer . . . . . . . . . . . 75
4.2.1 Generating a Behavioral View . . . . . . . . . . . . 75
4.2.2 Simulating a Behavioral View . . . . . . . . . . . . 78
4.3 Stand-Alone Verilog Simulation . . . . . . . . . . . . . . . 79
4.3.1 Verilog-XL . . . . . . . . . . . . . . . . . . . . . . 80
CONTENTS Draft August 24, 2006
4.3.2 NC Verilog . . . . . . . . . . . . . . . . . . . . . 86
4.3.3 vcs . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.4 Timing in Verilog Simulations . . . . . . . . . . . . . . . . 98
4.4.1 Behavioral versus Transistor Switch Simulation . . . 98
4.4.2 Behavioral Gate Timing . . . . . . . . . . . . . . . 101
4.4.3 Standard Delay Format (SDF) Timing . . . . . . . . 104
4.4.4 Transistor Timing . . . . . . . . . . . . . . . . . . . 106
5 Virtuoso Layout Editor 113
5.1 An Inverter Schematic . . . . . . . . . . . . . . . . . . . . 113
5.2 Layout for an Inverter . . . . . . . . . . . . . . . . . . . . . 116
5.2.1 Virtuoso Command Overview . . . . . . . . . . . 132
5.3 Printing Layouts . . . . . . . . . . . . . . . . . . . . . . . . 135
5.4 Design Rule Checking . . . . . . . . . . . . . . . . . . . . 135
5.4.1 DIVA Design Rule Checking . . . . . . . . . . . . 137
5.5 Generating an Extracted View . . . . . . . . . . . . . . . . 141
5.6 Layout Versus Schematic Checking . . . . . . . . . . . . . 141
5.6.1 Generating an analog-extracted view . . . . . . . . 152
5.6.2 Overall Cell Design Flow (so far...) . . . . . . . . . 152
5.7 Standard Cell Template . . . . . . . . . . . . . . . . . . . . 152
5.7.1 Standard Cell Geometry Specification . . . . . . . . 154
5.7.2 Standard Cell I/O Pin Placement . . . . . . . . . . . 159
5.7.3 Standard Cell Transistor Sizing . . . . . . . . . . . 160
6 Spectre Analog Simulator 165
6.1 Simulating a Schematic . . . . . . . . . . . . . . . . . . . . 167
6.1.1 Simulation with the Spectre Analog Environment . . 171
6.2 Simulating with a Config View . . . . . . . . . . . . . . . . 176
6.3 Mixed Analog/Digital Simulation . . . . . . . . . . . . . . 179
6.3.1 Final Words about Mixed Mode Simulation . . . . . 193
6.4 DC Simulation . . . . . . . . . . . . . . . . . . . . . . . . 195
4
Draft August 24, 2006 CONTENTS
6.4.1 Parametric Simulation . . . . . . . . . . . . . . . . 197
7 Cell Characterization 203
7.1 Characterization with Spectre . . . . . . . . . . . . . . . . . 203
7.2 Characterization with SignalStorm . . . . . . . . . . . . . . 203
7.3 Liberty (.lib) file format . . . . . . . . . . . . . . . . . . . . 203
8 Verilog Synthesis 205
8.1 Synopsys Synthesis: dc shell . . . . . . . . . . . . . . . . . 205
8.2 Synopsys Module Compiler . . . . . . . . . . . . . . . . . 205
8.3 Cadence BuildGates . . . . . . . . . . . . . . . . . . . . . . 205
8.4 Cadence to Synopsys (CSI) Interface . . . . . . . . . . . . . 206
9 Abstract Generation 207
9.1 Abstract Tool . . . . . . . . . . . . . . . . . . . . . . . . . 207
9.2 LEF File Generation . . . . . . . . . . . . . . . . . . . . . 207
10 SOC Encounter Place and Route 209
10.1 Encounter GUI . . . . . . . . . . . . . . . . . . . . . . . . 209
10.2 Encounter Scripting . . . . . . . . . . . . . . . . . . . . . . 209
11 Chip Assembly 211
11.1 Importing the Design to DFII . . . . . . . . . . . . . . . . . 211
11.2 Pad Frames in Encounter . . . . . . . . . . . . . . . . . . . 211
11.3 Pad Frames in CCAR . . . . . . . . . . . . . . . . . . . . . 211
11.4 Final GDS Generation . . . . . . . . . . . . . . . . . . . . 211
12 Design Example: TinyMIPS 213
12.1 MIPS: Synthesis . . . . . . . . . . . . . . . . . . . . . . . . 213
12.2 MIPS: Place and Route . . . . . . . . . . . . . . . . . . . . 213
12.3 MIPS: Simulation . . . . . . . . . . . . . . . . . . . . . . . 213
12.4 MIPS: Final Assembly . . . . . . . . . . . . . . . . . . . . 213
5
CONTENTS Draft August 24, 2006
A Tool Administration 215
A.1 Installing Cadence Tools . . . . . . . . . . . . . . . . . . . 215
A.2 Installing the NCSU CDK . . . . . . . . . . . . . . . . . . 215
A.3 Installing Synopsys Tools . . . . . . . . . . . . . . . . . . . 215
B Highlights of the Tools 217
B.1 ICFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
B.2 Composer Schematics . . . . . . . . . . . . . . . . . . . . . 218
B.3 Verilog Simulation . . . . . . . . . . . . . . . . . . . . . . 218
B.4 Spectre Analog Simulation . . . . . . . . . . . . . . . . . . 218
B.5 Virtuoso Layout . . . . . . . . . . . . . . . . . . . . . . . . 218
B.6 Abstract Generation . . . . . . . . . . . . . . . . . . . . . . 218
B.7 SignalStorm Library Characterization . . . . . . . . . . . . 218
B.8 SOC Encounter . . . . . . . . . . . . . . . . . . . . . . . . 218
B.9 Synopsys Synthesis . . . . . . . . . . . . . . . . . . . . . . 218
B.10 ICC Chip Assembly Router . . . . . . . . . . . . . . . . . . 218
C Tool and Setup Scripts 219
C.1 Cadence Setup Scripts . . . . . . . . . . . . . . . . . . . . 219
C.2 Synopsys Setup Scripts . . . . . . . . . . . . . . . . . . . . 219
C.3 TCL script basics . . . . . . . . . . . . . . . . . . . . . . . 219
C.4 Cadence Tool Scripts . . . . . . . . . . . . . . . . . . . . . 219
C.4.1 SOC Encounter . . . . . . . . . . . . . . . . . . . . 219
C.4.2 BuildGates Synthesis . . . . . . . . . . . . . . . . . 219
C.5 Synopsys Tool Scripts . . . . . . . . . . . . . . . . . . . . . 219
C.5.1 dc shell Synthesis . . . . . . . . . . . . . . . . . . 219
C.5.2 Module Compiler Synthesis . . . . . . . . . . . . . 219
C.5.3 PrimeTime Timing Analysis . . . . . . . . . . . . . 219
D MOSIS SCMOS rev8 Design Rules 221
6
Draft August 24, 2006 CONTENTS
E Technology and Cell Libraries 223
E.1 NCSU CDK . . . . . . . . . . . . . . . . . . . . . . . . . . 223
E.1.1 UofU Extensions . . . . . . . . . . . . . . . . . . . 223
E.2 Standard Cell Libraries . . . . . . . . . . . . . . . . . . . . 223
E.2.1 UofU Digital . . . . . . . . . . . . . . . . . . . . . 223
E.2.2 UofU Async . . . . . . . . . . . . . . . . . . . . . 223
E.2.3 OSU Libraries . . . . . . . . . . . . . . . . . . . . 223
Bibliography 224
Index 226
7
CONTENTS Draft August 24, 2006
8

数字VLSI芯片设计——使用Cadence和Synopsys_CAD工具(英文版).rar (13.59 MB, 下载次数: 2626 )