一个ncsim编译的诡异报错

iamyuchenjie · 发表于 2014-12-27 07:05:10

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本帖最后由 iamyuchenjie 于 2014-12-27 07:09 编辑

module async_fifo_ack (wclk,
rclk,
wa_reset_h,
ra_reset_h,
write_en,
write_data,
read_en,
read_data,
full,
empty
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 4;
input wclk;
input rclk;
input wa_reset_h;
input ra_reset_h;
input write_en;
input [DATA_WIDTH - 1:0] write_data;
input read_en;
output [DATA_WIDTH - 1:0] read_data;
output full;
output empty;
reg [DATA_WIDTH - 1:0] ram[0:( 1 << ADDR_WIDTH ) - 1];
reg [ADDR_WIDTH - 1:0] raddr_temp;
reg [ADDR_WIDTH - 1:0] int_waddr;
(* ASYNC_REG = "TRUE" *)
reg [ADDR_WIDTH:0] waddr_sync_0;
(* ASYNC_REG = "TRUE" *)
reg [ADDR_WIDTH:0] waddr_sync_1;
reg [ADDR_WIDTH:0] wbin;
reg [ADDR_WIDTH - 1:0] int_raddr;
(* ASYNC_REG = "TRUE" *)
reg [ADDR_WIDTH:0] raddr_sync_0;
(* ASYNC_REG = "TRUE" *)
reg [ADDR_WIDTH:0] raddr_sync_1;
reg [ADDR_WIDTH:0] rbin;
wire int_write_en;
wire [ADDR_WIDTH:0] next_wbin;
wire [ADDR_WIDTH:0] next_rbin;
wire [ADDR_WIDTH:0] raddr;
wire [ADDR_WIDTH:0] waddr;
// fifo memory
generate
if ( ( 1 << ADDR_WIDTH ) * DATA_WIDTH > 512 )
begin : FifoBlockRAM_AddrGen
always @(rbin or read_en or empty or next_rbin)
begin
raddr_temp = rbin[ADDR_WIDTH - 1:0];
end
end
else
begin : FifoDistributedRAM_AddrGen
always @(posedge rclk)
begin
raddr_temp <= rbin[ADDR_WIDTH - 1:0];
end
end // else: !if( ( 1 << ADDR_WIDTH ) * DATA_WIDTH > 512 )
endgenerate
generate
if ( ( 1 << ADDR_WIDTH ) * DATA_WIDTH > 512 )
begin : FifoBlockRAM_Mem
reg [ADDR_WIDTH - 1:0] raddr_reg;
always @(posedge wclk)
begin
if ( int_write_en == 1'b1 )
ram[wbin[ADDR_WIDTH - 1:0]] <= write_data;
end
always @(posedge rclk)
begin
raddr_reg <= raddr_temp;
end
assign read_data = ram[raddr_reg];
end // block: FifoBlockRAM
else
begin : FifoDistributedRAM_Mem
always @(posedge wclk)
begin
if ( int_write_en == 1'b1 )
ram[wbin[ADDR_WIDTH - 1:0]] <= write_data;
end
assign read_data = ram[raddr_temp];
end // block: FifoDistributedRAM
endgenerate
// write address synchronizer
always @(posedge rclk or posedge ra_reset_h)
begin
if ( ra_reset_h == 1'b1 )
begin
waddr_sync_0 <= {ADDR_WIDTH+1{1'b0}};
waddr_sync_1 <= {ADDR_WIDTH+1{1'b0}};
end
else
begin
waddr_sync_0 <= waddr;
waddr_sync_1 <= waddr_sync_0;
end
end // always @ (posedge rclk or posedge ra_reset_h)
// read address synchronizer
always @(posedge wclk or posedge wa_reset_h)
begin
if ( wa_reset_h == 1'b1 )
begin
raddr_sync_0 <= {ADDR_WIDTH+1{1'b0}};
raddr_sync_1 <= {ADDR_WIDTH+1{1'b0}};
end
else
begin
raddr_sync_0 <= raddr;
raddr_sync_1 <= raddr_sync_0;
end
end // always @ (posedge wclk or posedge wa_reset_h)
assign next_rbin = rbin + {{ADDR_WIDTH{1'b0}}, 1'b1};
// read address register
always @(posedge rclk or posedge ra_reset_h)
begin
if ( ra_reset_h == 1'b1 )
begin
rbin <= {ADDR_WIDTH+1{1'b0}};
int_raddr <= {ADDR_WIDTH{1'b0}};
end
else if ( read_en == 1'b1 && empty == 1'b0 )
begin
rbin <= next_rbin;
int_raddr <= next_rbin[ADDR_WIDTH:1] ^
next_rbin[ADDR_WIDTH - 1:0];
end
end // always @ (posedge rclk or posedge ra_reset_h)
assign int_write_en = ~full & write_en;
assign next_wbin = wbin + {{ADDR_WIDTH{1'b0}}, 1'b1};
// write address register
always @(posedge wclk or posedge wa_reset_h)
begin
if ( wa_reset_h == 1'b1 )
begin
wbin <= {ADDR_WIDTH+1{1'b0}};
int_waddr <= {ADDR_WIDTH{1'b0}};
end
else if ( int_write_en == 1'b1 )
begin
wbin <= next_wbin;
int_waddr <= next_wbin[ADDR_WIDTH:1] ^
next_wbin[ADDR_WIDTH - 1:0];
end
end // always @ (posedge wclk or posedge wa_reset_h)
// final gray-encoded read address
assign raddr = {rbin[ADDR_WIDTH], int_raddr};
// fifo empty indicator
assign empty = ( raddr == waddr_sync_1 );
// final gray-encoded write address
assign waddr = {wbin[ADDR_WIDTH], int_waddr};
// fifo full indicator
assign full = ( waddr[ADDR_WIDTH - 2:0] == raddr_sync_1[ADDR_WIDTH - 2:0] ) &&
( waddr[ADDR_WIDTH] != raddr_sync_1[ADDR_WIDTH] ) &&
( waddr[ADDR_WIDTH - 1] != raddr_sync_1[ADDR_WIDTH - 1] );
endmodule // async_fifo_ack

复制代码

modelsim编译通过没有问题
但是ncsim编译却报错！
ncvlog async_fifo_ack.v
ncvlog: *E,UMGENE (async_fifo_ack.v,66|8): An 'endgenerate' is expected [12.1.3(IEEE 2001)].

shiweishiwei · 发表于 2015-5-6 21:42:42

学些顶贴！！！！！！！！！

卡莫拉内西 · 发表于 2015-7-9 21:47:17

编译器不支持，更新NCsim的版本

amarnath1683 · 发表于 2016-5-25 06:31:41

how to remove the warning messages

Andy126 · 发表于 2018-12-14 15:54:51

[求助] 一个ncsim编译的诡异报错

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