Cadence 招聘资深前端验证/设计工程师

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Cadence招聘资深前端验证/设计工程师

Title: Principal/Lead/SeniorVerification Engineer (数字前端验证)

Location： SH/BJ

更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘

If you haveinterest, PLS send your update CV to zhangyl@cadence.com

  

Position Description:

Deliver/implement advanced verification solutions by utilizingCadence’s Incisive Verification product portfolio. The engineer should be ableto act as a strong team member and contributor, leading team projects andinitiatives. Exercise judgment within generally defined practices and policies.

Specific duties include:

-- Deep understanding on asic/SOC design flow

-- Excellent knowledge of advanced verification methodology likeeRM/OVM/UVM

-- Familiar with Cadence’s Incisive Plan to Closure Methodology (IPCM)

--Proficiency in System verilog, System C and/or e (Specman)

-- Developing and using Verification Components (eVC, OVC, UVC, VIP)

-- Developing and using assertion based verification and formalanalysis methods

--Skilled in scripting language, such as Perl, C shell, Makefile

-- Assessing the project verification requirements

-- Operating in a lead role regarding architecting and implementationof project   

     verificationenvironment/solution.

-- May coordinate/lead others within the scope of a defined project

Position Requirements:

-- Must have BS degree with 6+ years of applicable experience, MS degreewith 4+ years of applicable experience in electrical engineering,microelectronics, comparable engineering science or solid state physics.

-- Essential that the individual demonstrates strong communication,verbal and written. Requires good communication skills in English.

Desirable Qualifications:

-- A minimum of seven years relevant experience in industry.

-- Will have demonstrated hands-on experience and expertise withCadence verification design tools or equivalent tools, flows and methodologiesrequired to execute a verification project.

-- Will have demonstrated successful completion of 10+ verificationprojects as an individual contributor

-Prefer to have DDR IP verification experience

Title: Lead/Senior Design Engineer (数字前端设计)

Location: SH/BJ

更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘

If you have interest, PLS send your update CV to zhangyl@cadence.com

Position Description:

Deliver/implementDDR IP. The engineer should be able to act as a strong team member andcontributor, leading team projects and initiatives. Exercise judgment withingenerally defined practices and policies.

Specific duties include:

- Beresponsible for building and leading a high-performance IC design team, owningthe IC micro-architecture, package and test platform development, refining theEDA design flow

-Proficiency in logic design, simulation, synthesis, STA and testing

-Proficiency in Verilog and its simulation environment

- Goodknowledge of IC design

* At leastfive years experience driving complex IC development projects, excellentcommunication skills and the uncanny ability to both lead and contribute in acooperative team environment.

  

Position Requirements:

1. EssentialQualifications: Must have BS degree with 6+ years of applicable experience, MSdegree with 4+ years of applicable experience in electrical engineering,microelectronics, comparable engineering science or solid state physics.

2. Essentialthat the individual demonstrates strong communication, verbal and written. 3. Requiresgood communication skills in English.

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