【Marvell Cellular手机部门】招聘ASIC工程师

Hwangbo

1、Job Title: ASICImplementation Engineer

Location: Shanghai/Beijing

Job Description:

- Block, IP macro or SoC levelimplementation in 28nm or 20nm TSMC/UMC process

- UPF Synthesis with Synopsys DC orDCT/G flows

- RTL2Gate and Gate2Gate formal checkwith LEC and/or formality tools.

- Working with BE team to timingclosure in Primetime-SI on multi-corners and multi-modes

-
Ability to build or perfect theEDA-methodology-flow with perl, tcl or shell

- Knowledge on DFT (mbist/scan) will bean added advantage

Qualifications:

- BSEE degree or above

- Strong understandingof synthesis flow using DC/DCT/DCG - for a low power (UPF) and high speed-complex SoC

- Hands on experiencewith formal verification tools such as LEC and/or formality

- Must have the CTSconceptions in ICC at P&R stage
- Strong STA skills. Must have thorough knowledge on closing timing at unit andtop level

- Experience in mbistand scan will be plus

- Proficient in Perl,Tcl and Shell programming

-Good team work spirit

2、Job Title: ASIC DFT design Engineer

Location: Shanghai/Beijing

Job Description:

-Block, IP and SoC level DFTimplementation (JTAG, Scan, Mbist and analog/IP test etc.) and RTL integration;

-Participate in test spec/plandefinition; create the DFT design document and signoff DFT reviewchecklists;

-Test patterns/vectors generation andverification;

-Interface to backend team on physicaldesign and timing closure;

-Interface to test engineers on ATE andvectors bring-up and debugging;

-Chip DFT quality sign-off

-DFT STA, constraint generation, formaland timing closure

Qualifications:

- DFT design andintegration experience

- Hands on DFTimplementation experience (Bscan, Mbist, DC/AC Scan, analog IP test circuit integration,IDDQ test, ATPG and test pattern verification)

- Expertise with DFTtools from Synopsy, Mentor, Syntest etc.

- Strong logic designand verification background

- Experience inSynthesis and STA will be plus

- Proficient in Perl,tcl and shell programming

- BSEE degree or above

- Good team workspirit

3、Job Title: Cellphone Modem & SOC ASIC  Engineer

Location: Shanghai/Beijing

Job Description: modem:

3G: TD-SCDMA and WCDMA modem development
4G: TD-LTE modem development
SoC: next generation cellphone SoC full design cycle from spec.to massproduction. Largest chip inside Marvell.
1) R&D L2/L3 of the above protocol stacks.
2) Integration and Testing with the UE system.

Qualification:
MS degree in microelectronics, or electrical engineering.
At least three years working experience.
Experience in real design projects (front-end or backend) is a strong plus.
Good team work spirit and communication skill. Eager to learn, work and grow ina challenging project.

If you are interested in the position, please send your resume to the following email address:   jiangrr@marvell.com

Subject of your email should be: School_Name_Applied position_Information source
Eg.SJTU_Zhang Peng _Data Analyst_BBS