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写了一个16位乘法器,生成testbench文件,照着特权同学的书修改testbench如下,但是联合modelsim仿真发现无任何信号,为什么?点击run-all后也无反应。本人刚学FPGA,菜鸟一枚,求指教!多谢!
mux16 i1 (
// port map - connection between master ports and signals/registers
.ain(ain),
.bin(bin),
.clk(clk),
.done(done),
.rst_n(rst_n),
.start(start),
.yout(yout)
);
initial
begin
clk=0;
forever
#10 clk=~clk;
end
integer i,j;
integer wrong_timer;
integer txt_file;
initial begin
start=1'b0; //
ain=16'd0;
bin=16'd0;
wrong_timer=0;
txt_file=$fopen("txt_file.txt");
//
rst_n=1'b0;
#1000;
rst_n=1'b1;
$fdisplay(txt_file,"testbench is running!\n");
for(i=0;i<16'hffff;i=i+1) begin
for(j=0;j<16'hffff;j=j+1)begin
mux_task(i,j);
end
end
$fdisplay(txt_file,"%d wrong!\n",wrong_timer);
$fdisplay(txt_file,"testbench is over!");
$stop;
end
reg [31:0] mux_result;
task mux_task;
input [15:0] mux_a;
input [15:0] mux_b;
begin
ain=mux_a;
bin=mux_b;
@(posedge clk);
#2 start=1;
@(posedge done);
@(posedge clk);
#2 mux_result =yout;
@(posedge clk);
#2 start=0;
@(posedge clk);
end
endtask
always @(posedge done) begin
@(posedge clk);
@(posedge clk);
$fdisplay (txt_file,"ain=%d,bin=%d,yout=%d\t",ain,bin,mux_result);
if (ain*bin==yout) $fdisplay(txt_file,"right\n");
else begin
$fdisplay(txt_file,"wrong\n");
worng_timer=wrong_timer+1;
end
@(posedge clk);
end
endmodule
无任何信号???
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